參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 23/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝： 24
系列： *
其它名稱： 88K8483BRI
119 of 162
October 20, 2006
IDT IDT88K8483
SPI-4 Egress Data Clock Timing Register
SPI-4 Egress Status Timing Register
Field
Read /
Write
Bits
Length Reset
State
Description
DCTC[0:3]
R/W
0:0-0:3
4
0
This register is used to manually align the phase of the SPI-4 egress data clock to
the data and control lanes by adding from 0.1 clock cycle to 0.9 clock cycles of
delay to the data clock output. Note that the clock delay value is not monotonically
related to the value encoded in the bit field [3:0].
DCTC [3:0] Used for adding 0.1 clock cycle units of output delay to the
SPI-4 egress data clock.
[3:0]=0=No added delay
[3:0]=1=Add 0.1 clock cycle of delay to the SPI-4 egress data clock.
[3:0]=3=Add 0.2 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=2=Add 0.3 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=7=Add 0.4 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=6=Add 0.5 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=4=Add 0.6 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=5=Add 0.7 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=F=Add 0.8 clock cycles of delay to the SPI-4 egress data clock.
[3:0]=E=Add 0.9 clock cycles of delay to the SPI-4 egress data clock.
Table 91 SPI-4 Egress Data Clock Timing Control (BlockBase=0x0900, Register Offset=0x2C)
Field
Read /
Write
Bits
Length Reset
State
Description
STC0[0:1]
R/W
0:0-0:1
2
0
This register is used to manually align the phase of the status lane n by adding from
0.1 clock cycle to 0.3 clock cycles of delay. The STC0[1:0] and STC0[1:0] fields are
valid only for LVDS status and are not used for LVTTL status.
STCn [1:0] Used for adding 0.1 clock cycle units of output delay to SPI-
4 egress status lane n.
[1:0]=0=No added delay.
[1:0]=1=Add 0.1 clock cycle of delay to status lane n.
[1:0]=2=Add 0.2 clock cycles of delay to status lane n.
[1:0]=3=Add 0.3 clock cycles of delay to status lane n.
STC1[0:1]
R/W
0:2-0:3
2
0
Table 92 SPI-4 Egress Status Timing Control (Block Base=0x0900, Register Offset=0x2D)
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