參數(shù)資料
型號(hào)： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 22/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88K8483BRI
118 of 162
October 20, 2006
IDT IDT88K8483
SPI-4 Bit Alignment Result Register
SPI-4 Egress Data Lane Timing Register
SPI-4 Egress Data Control Lane Timing Register
Field
Read /
Write
Bits
Length Reset
State
Description
TAP[7:0]
R/W
0:0-0:7
8
0
TAP[3:0] covers the range of taps from 0 to 8. TAP[7:4] covers the range of taps
from 5 to 14. The value selected from the counter register field C[n] Table 87, is writ-
ten into the TAP field. This is used to select the received bit stream from the 10
samples after the HISTOGRAM measure is launched.There are 19 registers in total.
Note: Please refer to SPI-4 Ingress Block Diagram (p. 43) and SPI-4 Egress State Block Diagram (p. 46) for bit alignment overview.
Table 88 SPI-4 Bit Alignment Result Register (Block Base=0x0900 Register Offset=0x0C-0x1E)
Field
Read /
Write
Bits
Length Reset
State
Description
DTC0[1:0]
R/W
0:0-0:1
2
0
This register is used to manually align the phase of data lane n by adding between
0.1 and 0.3 clock cycles of delay.
DTCn [1:0] is used for adding 0.1 clock cycle units of output delay to the SPI-
4 egress data lane n.
DTCn[1:0]=0=No added delay.
DTCn[1:0]=1=Add 0.1 clock cycle of delay to data lane n.
DTCn[1:0]=2=Add 0.2 clock cycles of delay to data lane n.
DTCn[1:0]=3=Add 0.3 clock cycles of delay to data lane n.
DTC1[1:0]
R/W
0:2-0:3
2
0
.R/W
2
0
DTC15[1:0]
R/W
3:6-3:7
2
0
Table 89
SPI-4 Egress Data Lane Timing Control (Block Base=0x0900, Register Offset=0x2A)
Field
Read /
Write
Bits
Length Reset
State
Description
CTLTC[1:0]
R/W
0:0-0:1
2
0
This register is used to manually align the phase of the control lane by adding
between 0.1 clock cycle and 0.3 clock cycles of delay.
CTLTC [1:0] Used for adding 0.1 clock cycle units of output delay to the
SPI-4 egress control output.
CTLTC[1:0]=0=No added delay.
CTLTC[1:0]=1=Add 0.1 clock cycle of delay to the control output.
CTLTC[1:0]=2=Add 0.2 clock cycles of delay to the control output.
CTLTC[1:0]=3=Add 0.3 clock cycles of delay to the control output.
Table 90
SPI-4 Egress Data Control Lane Timing Control (Block Base=0x0900, Register Offset=0x2B)
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