參數(shù)資料
型號: IDT88K8483BRI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 53/162頁
文件大?。?/td> 0K
描述: IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝: 24
系列: *
其它名稱: 88K8483BRI
146 of 162
October 20, 2006
IDT IDT88K8483
GPIO Level Register
There are 3 registers.
GPIO Link Table
There are 3 registers.
Version Number Register
Software Version Register
Field
Read /
Write
Bits
Length Reset
State
Description
LEVEL
R/W
0:0
1
This field controls the logical level on the GPIO pins.It indicates a logical high or a
logical low.
0: Logical low.
1: Logical high.
Table 160
GPIO Level Register (Block Base=0x8B00, Register Offset=0x13-0x15)
Field
Read /
Write
Bits
Length Reset
State
Description
ADDRESS
R/W
0:0- 1:7
16
0
This field defines the address of the bit to be selected.
BIT
R/W
2:0- 2:4
5
0
This field defines which bit is to be selected at the address defined in the field
ADDRESS.
REFLECT_EN
R/W
2:5
1
0
If this field is enabled, then the LEVEL field in Table 160 reflects the status of the
bit which is selected from the indirect address space.
0: Disable.
1: Enable.
Table 161
GPIO Link Table (Block Base=0x8B00, Register Offset=0x16-0x18)
Field
Read /
Write
Bits
Length Reset
State
Description
VER
R
0:0-0:7
8
0x01
This field indicates the version of the chip.
ID
R
1:0-1:7
8
0xff
This field indicates the chip ID.
Table 162
Version Number Register (Block Base=0x8B00, Register Offset=0x30)
Field
Read /
Write
Bits
Length Reset
State
Description
SW_VER
R
0:0-0:7
8
0x01
This field indicates the software version of the chip.
Table 163
Version Number Register (Block Base=0x8B00, Register Offset=0x32)
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