參數(shù)資料
型號: IDT88K8483BRI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 29/162頁
文件大?。?/td> 0K
描述: IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝: 24
系列: *
其它名稱: 88K8483BRI
124 of 162
October 20, 2006
IDT IDT88K8483
PFP Queue Weighting Enable Register
Field
Read /
Write
Bits
Length Reset
State
Description
WEIGHT_EN
R/W
0:0
1
0
This field selects which LID data needs to be transmitted first according to its priority
when non-satisfied status information is received in the FIFO status channel.
0: The egress server scheduler schedules the LIDs in the calendar to be serviced in
a two-priority round robin according to the starving, hungry and satisfied status of
each LID. A starving status sets the LID priority high, a hungry status sets the prior-
ity low.
1: The egress server schedules the LIDs with hungry or starving status to be ser-
viced in a two-priority round robin scheme mode according to a fixed priority
scheme. The status values of hungry and starving received in the egress status cal-
endar are merged into a single non-satisfied status. The priority of the LID can be
Note: Please refer to page 52 for a detailed explanation of PFP priority and scheduling.
Table 103 PFP Queue Weighting Enable Register
(Block Base=0x1700/0x1F00, Register Offset=0x02)
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