參數(shù)資料
型號: IDT88K8483BRI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 161/162頁
文件大?。?/td> 0K
描述: IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝: 24
系列: *
其它名稱: 88K8483BRI
98 of 162
October 20, 2006
IDT IDT88K8483
PFP M-T extract control register for module A
PFP M-T extract data register for module A
Interrupt Registers
Primary Interrupt Indication Register
Field
Read/
Write
Bits
Length
Reset
State
Description
DATA_AVAILABLE
R/W
0:0
1
0
This bit indicates the availability of data in the extract FIFO. If data is
available, then it is extracted from the FIFO.
Read 0: Data is not available in the FIFO.
Read 1: Data is available in the FIFO.
Write 0: Clears the FIFO.
Note: After data is extracted from the FIFO, a transfer extract event will be forwarded to the interrupt module.
Table 42 PFP M-T extract control register (Register Offset=0x6)
Field
Read/
Write
Bits
Length
Reset
State
Description
DATA
R
0:0-0:7
8
0
This field holds the content extracted from the FIFO.
Table 43 PFP M-T extract data register (Register Offset=0x7)
Field
Read /
Write
Bits
Length Reset
State
Description
MODULE_A
R/W
0:0
1
0
This field capture events in module A.
Read 0: Normal operation of module A.
Read 1: An event is captured in module A.
Write 1: This field is cleared.
MODULE_B
R/W
0:1
1
0
This field capture events in module B.
Read 0: Normal operation of module B.
Read 1: An event is captured in module B.
Write 1: This field is cleared.
COMMON
R/W
0:2
1
0
This field capture events in module M.
Read 0: Normal operation of module M.
Read 1: An event is captured in module M.
Write 1: This field is cleared.
Table 44 Primary Interrupt Indication Register
(Register Offset=0x08)
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