參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 84/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝： 24
系列： *
其它名稱： 88K8483BRI
28 of 162
October 20, 2006
IDT IDT88K8483
Pin Description Table
The following table lists the functions of the pins provided on the IDT88K8483. Some of the functions listed are multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Analog signals ending with “P” are defined as being positive. Analog signals ending with “N”
are defined as being negative. Digital signals ending with “B” are defined as being active, or asserted, when at a logic zero (low) level. All other digital
signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Symbol1
I/O
Type2
Function
Comments
SPI-4 Interface
Link
PHY
SPI4A_ED[15:0]_P
SPI4B_ED[15:0]_P
SPI4M_ED[15:0]_P
SPI4A_ED[15:0]_N
SPI4B_ED[15:0]_N
SPI4M_ED[15:0]_N
O
LVDS
Egress Data Bus. This data bus is used to carry egress payload data
and in-band control words.
TDAT[15:0]
RDAT[15:0]
SPI4A_EDCLK_P
SPI4B_EDCLK_P
SPI4M_EDCLK_P
SPI4A_EDCLK_N
SPI4B_EDCLK_N
SPI4M_EDCLK_N
O
LVDS
Egress Data Clock. This clock is associated with the egress data bus
(ED) and the control signal (ECTL).
TDCLK
RDCLK
SPI4A_ECTL_P
SPI4B_ECTL_P
SPI4M_ECTL_P
SPI4A_ECTL_N
SPI4B_ECTL_N
SPI4M_ECTL_N
O
LVDS
Egress Control. This signal is high when a control word is present on
the egress data bus (ED) and it is low otherwise.
TCTL
RCTL
SPI4A_ESTA[1:0]_P
SPI4B_ESTA[1:0]_P
SPI4M_ESTA[1:0]_P
SPI4A_ESTA[1:0]_N
SPI4B_ESTA[1:0]_N
SPI4M_ESTA[1:0]_N
I
LVDS
Egress FIFO Status LVDS. These signals are used to carry egress
round-robin FIFO status information, along with associated error detec-
tion and framing.
TSTAT[1:0]
RSTAT[1:0]
SPI4A_ESCLK_P
SPI4B_ESCLK_P
SPI4M_ESCLK_P
SPI4A_ESCLK_N
SPI4B_ESCLK_N
SPI4M_ESCLK_N
I
LVDS
Egress Status Clock LVDS. This clock is associated with the egress
FIFO status signals (ESTA).
TSCLK
RSCLK
SPI4A_ESTA_T[1:0]
SPI4B_ESTA_T[1:0]
SPI4M_ESTA_T[1:0]
ILVTTL
Pull-up
Egress FIFO Status LVTTL. These signals are used to carry egress
round-robin FIFO status information, along with associated error detec-
tion and framing.
TSTAT[1:0]
RSTAT[1:0]
SPI4A_ESCLK_T
SPI4B_ESCLK_T
SPI4M_ESCLK_T
ILVTTL
Pull-up
Schmitt Trigger
Egress Status Clock LVTTL. This clock is associated with the egress
FIFO status signals (ESTA_T).
TSCLK
RSCLK
Table 2 Pin Description (Part 1 of 5)
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IDT88P8341BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8341BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8344 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
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