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參數(shù)資料
| 型號： | IDT88P8344 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPI交換4 ×的SPI - 3至SPI - 4期1.0 |
| 文件頁數(shù)： | 15/98頁 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344 |
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IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
3.1.2 SPI-3 egress
- All fragments will be of a programmable equal length with the exception
of EOP fragment which may be shorter
LID to LP map
- 64 entries, one per LID, for each SPI-3 egress port
- LP enable control
Multiple burst enable
- Allows more than one burst to be sent to an LP.
Poll length
- For use when in Link mode and when using the packet level mode
- Causes polling of the PHY for the logical ports associated to LIDs ranging
from[0 up to POLL_LENGTH] to find logical ports that can accept data
- Range is 0-63
Loopback enable
- Enables loopback fromSPI-3 physical interface to same SPI-3 physical
interface for test purposes
Data memory egress control
The SPI-3 egress port descriptor table (block_base 0x1700) for both paths
out of the data memory. The function of the SPI-3 egress port descriptor table
(block_base 0x1700) is to define where data goes after exiting the main data
memory. There are four options configurable:
- SPI-3
- SPI-4
- Capture
- Discard
Maximum number of memory segments
- Defines the largest BUFFER available to a LP / LID
- Each segment is 256 bytes
- Range 1 – 508 in increments of one segment
SPI-3 egress interface configuration
SPI Exchange allows for a pause at least two cycles of E_FCLK between
successive transfers.
SPI Exchange allows for over clocking for a higher clock frequency
supported as opposed to the one defined by the SPI-3 implementation
agreement.
The Link mode is selected by the Link flag in the SPI-3 general configuration
register.
The interface operates in PACKET mode or BYTE mode as defined by
the PACKET flag in the SPI-3 general configuration register.
SPI Exchange generates even or odd parity over E_DATA[7/31:0] on
the E_PRTY signal as defined by the EVEN flag in the Table 50, SPI-3 general
configuration register (register_offset=0x00).
SPI Exchange optionally generates two dummy cycles after assertion of
the STX signal. The option is enabled by the STX_SPACING flag in the Table
50, SPI-3 general configuration register (register_offset=0x00).
SPI Exchange optionally generates two dummy cycles after assertion of
an EOP signal. The option is enabled by the EOP_SPACING flag in the Table
50, SPI-3 general configuration register (register_offset=0x00).
SPI-3 egress interface errors
A clock available process detects an E_FCLK cycle within a 64 MCLK clock
cycle period. The result of this process is reported in the E_FCLK_AV flag in
Table 58,
SPI-3 egress fill level register (Block_base 0x0700 +
Register_offset=0x03)
.
A status change fromthe clock available status to the clock not available status
generates a maskable SPI-3 egress clock unavailable interrupt indication,
SPI3_ECLK_UN, in Table 62-Non LID associated interrupt indication register
(Block_Base 0x0C00 + Register_offset 0x0C).
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| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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