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參數(shù)資料
| 型號： | IDT88P8344 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPI交換4 ×的SPI - 3至SPI - 4期1.0 |
| 文件頁數(shù)： | 33/98頁 |
| 文件大?。?/td> | 601K |
| 代理商： | IDT88P8344 |
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33
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
4.3 SPI-3 ingress to SPI-3 egress datapath
The SPI-3 redirect buffer can store SPI-3 packet fragments. The status of the
packet fragment buffers is forwarded to the associated packet fragment proces-
sor. The purpose of the SPI-3 redirect is to enable per-LP flows between
physical interfaces SPI-3 A and SPI-3 B; as well as between SPI-3 C and SPI-
3 D. Other flows between SPI-3 ports are not allowed;
i.e
., between A and A,
A and C, A and D, B and B, B and C, B and D, C and C, and D and D.
The following is a description of the path taken by a fragment of data through
the device.
SPI-3 modules are implemented in pairs (ports A & B or C & D). A SPI-3 to
SPI-3 path is between an LP on one SPI-3 to the paired SPI-3. Data enters on
the SPI-3 interface in fragments. Fragments are of equal length except the last
fragment of a packet which may be shorter. The LP address is in-band with the
data. The packet fragment enters an ingress buffer. SPI-3 LP address, error
information, SOP, and EOP information is are stored with the fragment. The LP
address is mapped to a LID. The fragment is stored in buffer segment pool per-
LID-allocated memory space.
The Table 80, SPI-3 egress port descriptor table (64 entries) is consulted,
and the PFP decides to send a LID to the associated SPI-3 egress port. The
SPI-3 packet fragment processor chooses the next LP. The choice of LP is
dependent on status of the LP and availability of a complete fragment. Data is
moved to an egress buffer along with the SPI-3 LP address, error information,
SOP, and EOP information. Data is transmtted in packet fragments over a SPI-
3 interface.
The paths to and fromthe mcroprocessor interface can be used to perform
mappings froma SPI-3 LP to a SPI-3 LP where not provided, and froma SPI-
4 to a SPI-4 LP. However these paths are limted by the bandwidth of the
mcroprocessor interface.
The diagrambelow shows the datapath through the device froma SPI-3
interface to its paired SPI-3 interface. For the SPI-3 redirect, the LID connecting
associated port pairs must be the same in both directions.
Figure 21. SPI-3 ingress to SPI-3 egress datapath
…
SPI-3 /
LID map
…
…
SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
SPI-4.2
Min: 80 MHz
Max: 400 MHz
JTAG
uproc
Chip Counters Memory
LID Counters Memory
I
SPI-4 /
LID map
SPI-3 /
LID map
LID Counters Memory
Main
Memory
A
Main
Memory
B
6370 drw14
I
I
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