參數(shù)資料
型號： IDT88P8344
廠商： Integrated Device Technology, Inc.
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPI交換4 ×的SPI - 3至SPI - 4期1.0
文件頁數(shù)： 24/98頁
文件大?。?/td> 601K
代理商： IDT88P8344
24
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
DATAPATH CONFIGURATION
A logical view of datapath configuration using Packet Fragment Processors
is shown in Figure 12,
Logical View of Datapath Configuration Using PFPs
.
Two PFPs are associated with each SPI-3 port, one for ingress and one for
egress. Logical ports are mapped internally into Logical Identifiers (“LIDs”, “LID
Map”) for the control of each per-LID data flow to each physical port, logical port,
memory queue size, and backpressure threshold (watermark), by program-
mng the LID register files.
Figure 12. Logical view of datapath configuration using PFPs
[LID] = LP | EN | BRV
SPI-3 Egress LID to LP Map (one of four: ABCD)
[LP] = LID | EN | BRV
SPI-3 Ingress LP to LID Map (one of four: ABCD)
[LID] = LP | EN
SPI-4 INGRESS DATA
SPI-4 EGRESS DATA
[LP] = LID | PPE | EN
LID
BRV
EN
LP
BRV
EN
LP
EN
256 LIDs
SPI-4 Egress LID to LP Map
PFP AND MEMORY
((OPFP AND MEMORY
((ONE OF FOUR: ABCD)
PPFP AND MEMORY
((OPFP AND MEMORY
((ONE OF FOUR: ABCD)
SPI-3 INGRESS DATA (ONE OF FOUR)
SPI-3 EGRESS DATA (ONE OF FOUR)
LID
EN
A/B/
C/D
256 LPs
SPI-4 Ingress LP to LID Map
256 LPs
64 LIDs
6370 drwXB
LID - Logical Identifier
EN - LID enable flag
BRV - Bit reversal
LP - Logical port
PFP - Packet fragment processor
相關(guān)PDF資料
PDF描述
IDT88P8344BHGI SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
IDTAMB0480 ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM MODULES
IDTCSP2510DPGI 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
IDTCSP2510DPG SENSOR OPTICAL SLOTTED 1.0MM
IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
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