參數(shù)資料
型號(hào)： IDT88P8344
廠商： Integrated Device Technology, Inc.
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPI交換4 ×的SPI - 3至SPI - 4期1.0
文件頁(yè)數(shù)： 52/98頁(yè)
文件大?。?/td> 601K
代理商： IDT88P8344
52
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
Software reset
TABLE 39 - SOFTWARE RESET REGISTER (0x20 in
the direct accessed space)
Field
Bits
SW_RESET
0
INIT_DONE
1
Reserved
7:2
The SPI-4 Status Register (0x22 in the direct accessed space) has read
access, and interrupt status fields are cleared by a mcroprocessor write cycle,
where a logical one must be written to clear the field(s) targeted.
The SPI-4 Status Register is a secondary interrupt status register and can
only be active if the SPI-4 field is active in the Primary Interrupt Status Register
(Direct 0x2C).
I_DIP_ERR_I
0=No errors
1=One or more DIP-4 errors have been registered on the SPI-4 ingress
SPI-4 ingress DIP-4 error interrupt indication.
I_SYNCH_I
synchronization to in synchronization condition interrupt indication.
0=No detection, still not in synchronization
SPI-4 ingress data path has transitioned fromout of
1=Transition fromout of synchronization to in synchronization, or transition
fromin synchronization to out of synchronization
I_BUS_ERR_I
SPI-4 ingress bus error interrupt indication.
0=No errors
1=One or more bus errors have been registered on the SPI-4 ingress
SPI4_INACTIVE_TRANSFER_I
rupt indication.
0=No indication
1=One or more inactive transfers have been registered on the SPI-4 ingress
SPI-4 ingress inactive transfer inter-
DCLK_UN_I
to an unavailable condition interrupt indication.
0=No detection, I_DCLK is available
1=I_DCLK transitioned fromavailable to an unavailable state
SPI-4 ingress data clock has transitioned fromavailable
E_DIP_ERR_I
SPI-4 egress DIP-2 error interrupt indication on the SPI-
4 egress status channel.
0=No errors
1=One or more DIP-2 errors have been registered
E_SYNCH_I
synchronization to an in synchronization condition interrupt indication.
0=No detection, still not in synchronization
1=Transition fromout of synchronization to in synchronization, or transition
fromin synchronization to out of synchronization
SPI-4 egress status channel has transitioned fromout of
SCLK_UN_I
to an unavailable condition interrupt indication.
In LVTTL mode the Bridgeport does not detect the SPI-4 egress status clock
(E_SCLK_T). Therefore, for LVTTL mode the software should ignore the
SCLK_UN field in the SPI-4 Status Register.
0=No detection, E_SCLK is available
1=E_SCLK transitioned fromavailable to an unavailable state
SPI-4 egress status clock has transitioned fromavailable
SPI-4 enable register (0x23 in the direct accessed
space)
TABLE 41 - SPI-4 ENABLE REGISTER (0x23 IN
THE DIRECT ACCESSED SPACE)
The SPI-4 Enable Register (0x23 in the direct accessed space) has read
and write access. SPI-4 Enable Register is used to bitwise enable the interrupts
in the SPI-4 Status Register.
I_DIP4_ERR_EN
SPI-4 ingress DIP-4 error interrupt indication enable.
0=Disable DIP-4 error interrupt
1=Enable DIP-4 error interrupt
Field
Bits
Length
Initial Val
0
0
0
0
0
0
0
0
I_DIP4_ERR_EN
I_SYNCH_EN
I_BUS_ERR_EN
SPI4_INACTIVE_TRANSFER_EN
DCLK_UN_EN
E_DIP_ERR_EN
E_SYNCH_EN
SCLK_UN_EN
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
Field
Bits
0
1
2
3
4
5
6
7
Length
1
1
1
1
1
1
1
1
Initial Val
0
0
0
0
0
0
0
0
I_DIP_ERR_I
I_SYNCH_I
I_BUS_ERR_I
SPI4_INACTIVE_TRANSFER_I
DCLK_UN_I
E_DIP_ERR_I
E_SYNCH_I
SCLK_UN_I
TABLE 40 - SPI-4 STATUS REGISTER (0x22 IN THE
DIRECT ACCESSED SPACE)
Length
1
1
6
Initial Value
0
0
0
The software reset bit is writable fromthe direct accessed memory space.
Write a “1” to the SW_RESET bit to initiate the software reset. The SW_RESET
bit will clear to a “0” after the chip has initialized itself. The INIT_DONE bit is set
to a “1” when the initialization following reset has completed. The software reset
is the same as the hardware. The Reserved field must be set to 0.
The Initial Value column in this document is the value of the register after reset
has completed.
SW_RESET
Setting the SW_RESET bit initiates a software reset of the chip.
The SW_RESET bit is self-clearing.
0=No operation is performed
1=Initiate a software reset
INIT_DONE
Status indication bit following a reset.
0=Chip has not completed initialization following reset
1= Chip has completed initialization following reset
SPI-4 status register (0x22 in the direct accessed
space)
相關(guān)PDF資料
PDF描述
IDT88P8344BHGI SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
IDTAMB0480 ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM MODULES
IDTCSP2510DPGI 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
IDTCSP2510DPG SENSOR OPTICAL SLOTTED 1.0MM
IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
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