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54
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
The primary interrupt status register (0x2C in the direct accessed space) has
read-only access. The interrupts for the primary interrupt status register must
be acknowledged by servicing the corresponding secondary interrupt status
registers.
MODULE_A
allowing an interrupt in the Module Status Register (secondary interrupt register
0x24).
0=No MODULE_A interrupt active
1=MODULE_A interrupt is active
When active, the MODULE_A field is responsible for
MODULE_B
allowing an interrupt in the module status register (secondary interrupt register
0x25).
0=No MODULE_B interrupt active
1=MODULE_B interrupt is active
When active, the MODULE_B field is responsible for
SPI-34_CAPTURE_EN
interrupt enable.
0=Disable capture interrupt
1=Enable capture interrupt
SPI-3 ingress to SPI-4 egress capture event
SPI-43_CAPTURE_EN
interrupt enable.
0=Disable capture interrupt
1=Enable capture interrupt
SPI-4 ingress to SPI-3 egress capture event
SPI-34_INSERT_EN
SPI-3 ingress to SPI-4 egress insert event interrupt
enable.
0=Disable insert interrupt
1=Enable insert interrupt
SPI-43_INSERT_EN
interrupt enable.
0=Disable insert interrupt
1=Enable insert interrupt
SPI-4 ingress to SPI-3 egress insert event
PMON_EN
0=Disable PMON interrupt
1=Enable PMON interrupt
Performance Monitor event interrupt enable.
Primary interrupt status register (0x2C in the
direct accessed space)
TABLE 44 - PRIMARY INTERRUPT STATUS REGIS-
TER (0x2C IN THE DIRECT ACCESSED SPACE)
MODULE_C
allowing an interrupt in the module status register (secondary interrupt register
0x26).
0=No MODULE_C interrupt active
1=MODULE_C interrupt is active
When active, the MODULE_C field is responsible for
MODULE_D
allowing an interrupt in the module status register (secondary interrupt register
0x27).
0=No MODULE_D interrupt active
1=MODULE_D interrupt is active
When active, the MODULE_D field is responsible for
SPI-4
When active, the SPI-4 field is responsible for allowing an interrupt
in the SPI-4 status register (secondary interrupt register 0x22).
0=No SPI-4 interrupt active
1=SPI-4 interrupt is active
SECONDARY
allowing an interrupt in the Secondary Interrupt Status Register (secondary
interrupt register 0x2D).
0=No SECONDARY interrupt active
1=SECONDARY interrupt is active
When active, the SECONDARY field is responsible for
Secondary interrupt status register (0x2D in the
direct accessed space)
TABLE 45 - SECONDARY INTERRUPT STATUS
REGISTER
(0x2D IN THE DIRECT ACCESSED SPACE)
Field
Bits
0
1
2
3
4
5
7:6
Length
1
1
1
1
1
1
2
Initial Value
0
0
0
0
0
0
0
MODULE_A
MODULE_B
MODULE_C
MODULE_D
SPI-4
SECONDARY
Reserved
Field
Bits
0
1
7:2
Length
Initial Value
0
0
0
TIME_BASE
INDIRECT_ACCESS
Reserved
1
1
6
The secondary interrupt status register (0x2D in the direct accessed space)
has read and write access.
The secondary interrupt status register has read access, and Interrupt status
fields are cleared by a mcroprocessor write cycle, where a logical one must
be written to clear the field(s) targeted.
The secondary interrupt status register is a secondary interrupt status register
and can only be active if the SECONDARY_EN field is active in the primary
interrupt enable register (Direct 0x2C).
TIME_BASE
0=No time base event
1=Time base has expired
Time base expiration interrupt indication.
INDIRECT_ACCESS
0=No indirect access event
1=Indirect access has completed
Indirect access completion interrupt indication.