參數(shù)資料
型號(hào)： IDT88P8344
廠商： Integrated Device Technology, Inc.
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPI交換4 ×的SPI - 3至SPI - 4期1.0
文件頁數(shù)： 37/98頁
文件大?。?/td> 601K
代理商： IDT88P8344
37
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
4.4.4 SPI-4 ingress to microprocessor interface
datapath
The diagrambelow shows the datapath through the device fromthe SPI-4
interface to the mcroprocessor data capture interface.
The following is a description of the path taken by a burst of data through the
device.
Data enters on the SPI-4 interface in bursts. Bursts are normally of equal
length except the last burst of a packet which may be shorter. The control word
is in-band with the data. The burst data enters a SPI-4 ingress buffer. SPI-4 LP
address, error information, SOP, and EOP are stored along with the burst data.
The SPI-4 LP address is mapped to a LID. Data is stored in per-LID allocated
buffer segments. The DIRECTION field of the SPI-3 egress port descriptor
(Block_base 0x1700 + Register_offset 0x00 - 0xFF) is used to send this LID
data to the mcroprocessor port. Data is moved to the capture buffer along with
the LP address, LID, error information, SOP, and EOP.
The data available bit is set by the PFP. Data and control information are read
fromthe capture buffer through the mcroprocessor interface.
Figure 29. SPI-4 ingress to microprocessor data capture interface path
…
…
JTAG
uproc
LID Counters Memory
4 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
I
Chip Counters Memory
I
SPI-3 /
LID map
Main
Memory
A
SPI-4.2
Min: 80 MHz
Max:400 MHz
SPI-4 /
LID map
6370 drw17
Figure 28. Mcroprocessor data capture buffer
6370 drw28
flags
length
data[1]
data[2]
data[255]
lid
data[0]
SOP
EA
ED
PAR
EOP
not used
EA
ED
PAR
data parity error
address parity error
packet error
7
0
i
t
t+1
t+258
e
t
t+1
t+258
相關(guān)PDF資料
PDF描述
IDT88P8344BHGI SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
IDTAMB0480 ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM MODULES
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