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參數(shù)資料
| 型號： | IDT88P8344 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPI交換4 ×的SPI - 3至SPI - 4期1.0 |
| 文件頁數(shù)： | 27/98頁 |
| 文件大?。?/td> | 601K |
| 代理商： | IDT88P8344 |
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IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
SPI-4 egress data bursts
The PFP produces fragments of up to N*16 bytes. N is defined by the
MAX_BURST_H or MAX_BURST_S parameter associated with each LID. For
a high priority (starving) LID the MAX_BURST_S parameter is used. For a low
priority (hungry) LID the MAX_BURST_H parameter is used. The PFP may
not fill the buffers to the level granted when a new segment needs to be used
in the SPI3-4 buffer memory or when the last fragment of a packet is copied into
the buffer. The information received over the FIFO status channel is interpreted
as status or credit information as selected by the CREDIT_EN flag in Table 78,
SPI-3 to SPI-4 flow control register (0x01). If the status mode is used, data will
be egressed until the status is changed. If the credit mode is used, the SPI-4
egress will issue only one credits worth data burst and then wait for another credit
fromthe status channel before issuing another LID burst.
SPI-4 egress FIFO status channel updates
The SPI-4 egress FIFO Status Channel
Module continuously verifies the
status information for the LIDs associated to SPI-4 logical ports. The PFP
searches and selects a LID, fetches the associated information and queues data
to the SPI-4 egress. The obsolete buffer segment is returned to the free buffer
segment pool (unless the repeat test feature is enabled). Searching the LID to
be served is performed for both a high priority and a low priority LID. The priority
is defined by the status received fromthe SPI-4 egress module.
SPI-3 ingress logical port mapping
Each of the four SPI-3 interfaces has an associated SPI-3 ingress LP to LID
map, (See Table 49) for the purpose of directing the packet fragments fromits
SPI-3 ingress to its associated SPI-3 ingress main memory buffer segment pool.
The SPI-3 LID map has 256 entries, one per SPI-3 LP, but only 64 LPs are
supported on any SPI-3 interface at any one time. Each SPI-3 interface has
an enable bit, as well as the ability to reverse the bit ordering of the interface.
The packet fragment length is associated with a SPI-3 interface. The allowed
range is 0 to 255 bytes per packet fragment. The last fragment of a packet can
be shorter than the programmed fragment size. Each SPI-3 port can be
independently set for either Link or PHY mode of operation.
SPI-3 ingress LID associated control
Each LID on a SPI-3 interface has the ability to be programmed for mnimum
and maximumpacket length. The mnimumpacket length can be set from0 to
255 bytes in one byte increments. The maximumpacket length can be set from
0 to 16,383 bytes in one byte increments. Each LID can be enabled and disabled
independently.
Figure 14. SPI-3 ingress LP to LID map
6370 drwXC
LID
BRV
EN
256 LPs
[LP] = LID | EN | BRV
LID: Logical Identifier
EN: LID Enable
BRV: Bit Reversal
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