參數(shù)資料
型號(hào)： IDT88P8344
廠商： Integrated Device Technology, Inc.
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPI交換4 ×的SPI - 3至SPI - 4期1.0
文件頁(yè)數(shù)： 36/98頁(yè)
文件大?。?/td> 601K
代理商： IDT88P8344
36
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
4.4.3 Microprocessor interface to SPI-4 egress
datapath
Packets can be inserted into the SPI-3-4 datapath by the mcroprocessor. The
following is a description of the path taken by a burst of data through the device.
Data and control information are written to the insert buffer through the
mcroprocessor interface. The data available bit is set. Data is stored in the insert
buffer along with the LP address, LID, error information, SOP, and EOP. Data
is stored in per-LID allocated buffer segments. The Table 36-SPI-3 data insert
control register is consulted, and determnes to send this LID to the SPI-4 egress
port. The SPI-4 Packet Fragment Processor chooses the next LP. Data is sent
to the SPI-4 egress buffer along with the SPI-4 LP address, error information,
SOP, and EOP. Data is transmtted in bursts over the SPI-4 egress interface.
The mcroprocessor needs to write data into a dedicated buffer to insert a
packet burst. Refer to Figure 26,
Mcroprocessor data insert buffer
for the data
format in the buffer. The mcroprocessor must verify the DATA_AVAILABLE flag
in the
SPI-4 insert control register
and waits until the flag is cleared. The
mcroprocessor specifies the EOP, SOP, ERROR, LID and LENGTH fields and
writes up to 256 bytes of packet fragment burst into the insert buffer. The packet
burst insert buffer is accessed through the Table 34, SPI-4 data insert register
(register_offsets 0x03, 0x0B, 0x13, 0x1B)
SPI-4 data insert register.
The
mcroprocessor hands over control of the buffer setting the DATA_AVAILABLE
flag in the
SPI-4 insert control register.
A
SPI4_insert_empty event
is generated
when the DATA_AVAILABLE flag is cleared. The event is directed towards the
interrupt module.
Figure 26. Mcroprocessor data insert buffer
6370 drw28
flags
length
data[1]
data[2]
data[255]
lid
data[0]
SOP
EA
ED
PAR
EOP
not used
EA
ED
PAR
data parity error
address parity error
packet error
7
0
i
t
t+1
t+258
e
t
t+1
t+258
Figure 27. Mcroprocessor data insert interface to SPI-4 egress datapath
…
…
JTAG
uproc
LID Counters Memory
4 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
I
Chip Counters Memory
I
SPI-3 /
LID map
Main
Memory
A
SPI-4.2
Min: 80 MHz
Max:400 MHz
SPI-4 /
LID map
6370 drw18
The diagrambelow shows the datapath through the device fromthe
mcroprocessor data insert interface to the SPI-4 egress interface.
相關(guān)PDF資料
PDF描述
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