參數(shù)資料
型號(hào)： IDT88P8344
廠商： Integrated Device Technology, Inc.
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPI交換4 ×的SPI - 3至SPI - 4期1.0
文件頁(yè)數(shù)： 28/98頁(yè)
文件大小： 601K
代理商： IDT88P8344
28
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
SPI-4 egress interface port associated control
The SPI-4 interface has an associated LID to LP map (See Table 101 - SPI-
4 egress LID to LP Map Block_base 0x0400 = Register_offset 0x00 - 0xFF)
for the purpose of directing the packet fragments fromthe selected SPI-3 ingress
main memory buffer segment pool to the SPI-4 egress interface. The SPI-4 LID
map has 256 entries, one per LID. The SPI-4 interface has an enable bit. The
burst length is associated with the SPI-4 interface. The allowed burst range is
16 to 256 bytes per burst. The last burst of a packet can be shorter than the
programmed burst size.
SPI-4 egress LID associated control
Each of the 256 entries in the SPI-4 egress LID to LP map (See Table 101
- SPI-4 egress LID to LP Map (256 entries)) is used to control the pulling of bursts
out of the buffer segment pool and into the SPI-4 egress interface. Each LID can
be enabled and disabled independently.
Figure 15. SPI-4 egress LID to LP map
6370 drwXD
LP
EN
256 LIDs
[LID] = LP | EN
Figure 16. SPI-3 ingress to SPI-4 egress datapath
…
…
JTAG
uproc
LID Counters Memory
4 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
I
Chip Counters Memory
I
SPI-3 /
LID map
Main
Memory
A
SPI-4.2
Min: 80 MHz
Max:400 MHz
SPI-4 /
LID map
6370 drw12
LP: Logical Port
EN: LP Enable
The diagrambelow shows the datapath through the device froma SPI-3
ingress interface to the SPI-4 egress interface.
相關(guān)PDF資料
PDF描述
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