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| 型號： | IDT88P8344 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPI交換4 ×的SPI - 3至SPI - 4期1.0 |
| 文件頁數(shù)： | 71/98頁 |
| 文件大?。?/td> | 601K |
| 代理商： | IDT88P8344 |
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71
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
SPI-4 ingress calendar configuration register
(Block_base 0x0300 + Register_offset 0x04 - 0x05)
TABLE 93 - SPI-4 INGRESS CALENDAR CONFIGU-
RATION REGISTER (0x04 to 0x05)
Field
Bits
I_CAL_M
7:0
I_CAL_LEN
13:8
Length
8
6
Initial Value
0
0x01
The SPI-4 ingress calendar configuration registers are at Block_base
0x0300 and have read and write access. The Register_offset for calendar_0
is 0x04. The Register_offset for calendar_1 is 0x05.
The bit fields of a SPI-4 ingress calendar configuration register are described.
Some devices have a fixed calendar length and a fixed calendar M while
the Bridgeport calendar length has to be multiply of 4, and the calendar Mis
programmable. Therefore, the user may need to add an FPGA between the
Bridgeport & the adjacent device SPI-4 status signals.
I_CAL_M
the calendar sequence is repeated before a DIP-2 parity and “1 1” framng
words are inserted. The actual calendar_Mvalue used is one more than the
value programmed into the I_CAL_Mfield.
The I_CAL_Mvalue programmed defines the number of times
I_CAL_LEN
the SPI-4 ingress calendar. The actual length of the calendar is four times the
value of one more than the I_CAL_LEN field: (I_CAL_LEN + 1)*4. For example,
if the I_CAL_LEN field is programmed to 0x04, the actual value used is 0x14.
The calendar length must be at least as large as the number of active SPI-4
ingress LPs.
The I_CAL_LEN value programmed defines the length of
SPI-4 ingress watermark register (Block_base
0x0300 + Register_offset 0x06)
SPI-4 ingress fill level register (Block_base 0x0300
+ Register_offset 0x07-0x0A)
There is one SPI-4 ingress fill level register per SPI-3 interface at Block_base
0x0300. Each register has read-only access.
The SPI-4 ingress fill level register for PFP A is at Block_base 0x0300 +
Register_offset 0x07.
The SPI-4 ingress fill level register for PFP B is at Block_base 0x0300 +
Register_offset 0x08.
The SPI-4 ingress fill level register for PFP C is at Block_base 0x0300 +
Register_offset 0x09.
The SPI-4 ingress fill level register for PFP D is at Block_base 0x0300 +
Register_offset 0x0A.
The bit field of a SPI-4 ingress fill level register is described.
TABLE 95 - SPI-4 INGRESS FILL LEVEL REGISTER
(0x07 to 0x0A)
Field
Bits
FILL_CUR
5:0
TABLE 94 – SPI-4 INGRESS WATERMARK REGIS-
TER (REGISTER_OFFSET 0x06)
Field
Bits
Length Initial Value
WATERMARK
4:0
5
reserved
7:5
3
WATERMARK
12:6
5
reserved
15:13
3
WATERMARK
20:16
5
reserved
23:21
3
WATERMARK
28:24
5
reserved
31:29
3
SPI-4 ingress Watermark Register is at Block_base 0x0300, Register_offset
0x06. The SPI-4 ingress Watermark Register has read and write access. A SPI-
4 interface can be set to a Watermark Value per PFP. 0x1F is the highest
watermark that can be set, meaning all ingress buffers will be full before
backpressure will be initiated on a SPI-4 ingress interface PFP. A WATER-
MARK field value of 0x0F is used to set a watermark for a half-full ingress buffer
before tripping backpressure. The units of WATERMARK are one-thirty-
second of the available ingress buffering per unit. Each unit is equal to 128 bytes.
Function
0x0D
0
0x0D
0
0x0D
0
0x0D
0
Watermark for PFP A
Watermark for PFP B
Watermark for PFP C
Watermark for PFP D
Length
6
Initial Value
0x0
TABLE 96 - SPI-4 INGRESS MAX FILL LEVEL
REGISTER (0x0B to 0x0E)
Field
Bits
FILL_MAX
5:0
There are four SPI-4 ingress max fill level registers, one per SPI-3 interface,
at Block_base 0x0300. Each register has read-only access, and is cleared after
reading. The value 0x20 is the highest filling level, meaning all ingress buffers
on a PFP had been full at some time since the last read of the FILL_MAX field.
The units of FILL_MAX are one-thirty-second of the available ingress buffering
per PFP. Each unit is equal to 128 bytes.
The SPI-4 ingress max fill level register for PFP A is at Block_base 0x0300
+ Register_offset 0x0B.
The SPI-4 ingress max fill level register for PFP B is at Block_base 0x0300
+ Register_offset 0x0C.
The SPI-4 ingress max fill level register for PFP C is at Block_base 0x0300
+ Register_offset 0x0D.
The SPI-4 ingress max fill level register for PFP D is at Block_base 0x0300
+ Register_offset 0x0E.
The bit field of a SPI-4 ingress max fill level register is described.
Length
6
Initial Value
0x00
FILL_MAX
MaximumSPI-4 ingress buffer fill level since the last read of the
SPI-4 ingress max fill level register.
SPI-4 ingress diagnostics register (Block_base
0x0300 + Register_offset 0x0F)
TABLE 97 - SPI-4 INGRESS DIAGNOSTICS REGIS-
TER (REGISTER_OFFSET 0x0F)
Field
Bits
I_FORCE_TRAIN
0
I_ERR_INS
1
I_DIP_NUM
5:2
Length
1
1
4
Initial Value
0
0
0
FILL_CUR
register, the value read fromit will change rapidly and is used for internal
diagnostics only.
Current SPI-4 ingress buffer fill level. Since this is a real-time
SPI-4 ingress max fill level register (Block_base
0x0300 + Register_offset 0x0B to 0x0E)
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