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參數(shù)資料
| 型號(hào)： | IDT88P8344 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPI交換4 ×的SPI - 3至SPI - 4期1.0 |
| 文件頁數(shù)： | 48/98頁 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344 |
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48
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
Block_base
0x0000
0x0100
0x0200
0x0300
0x0400
0x0500
0x0600
0x0700
0x0800
0x0900
Function
SPI-4 ingress LP to LID tables
SPI-4 ingress calendar_0
SPI-4 ingress calendar_1
SPI-4 ingress registers
SPI-4 egress LID to LP map
SPI-4 egress calendar_0
SPI-4 egress calendar_1
SPI-4 egress configuration and status registers
SPI-4 ingress timng block registers
PMON timebase control, clock generator control, GPIO register, and version number
TABLE 24 - INDIRECT ACCESS BLOCK BASES FOR COMMON MODULE
Register offset
The register offset is shown in the section where the register is defined. The
register offset is referred to as, “Register_offset”, in this document. A register
reference takes the formof, “[Register_offset 0xHH]”, where HH is the
hexadecimal value of the register offset.
Indirect register access
Indirect register write access
An indirect write access is initiated by first checking for IND_BUSY=0 in the
indirect access control register, and then writing data into the indirect access data
registers. Next, the address is written into the indirect access address registers.
Then, 0x00 is written into the indirect access control register. The status of the
IND_BUSY flag in the indirect access control register is checked to ensure the
process has completed before another indirect access can be initiated.
Indirect register read access
An indirect read access is initiated by first checking for IND_BUSY=0 in the
indirect access control register, and then writing the address into the indirect
access address registers. Then, 0x40 is written into the indirect access control
register. The status of the IND_BUSY flag in the indirect access control register
is checked to ensure the process has completed, and then data is read out from
the indirect access data registers.
The registers for controlling indirect register access are shown below. The
registers for controlling indirect register access are directly accessible with read
and write access.
TABLE 25 - INDIRECT ACCESS DATA REGISTERS
(DIRECT ACCESSED SPACE) AT 0x30 to 0x33
Field
Bits
Length
DATA[7:0]
7:0
DATA[15:8]
15:8
DATA[23:16]
23:16
DATA[31:24]
31:24
Function
8
8
8
8
Indirect Data Register 0x30
Indirect Data Register 0x31
Indirect Data Register 0x32
Indirect Data Register 0x33
TABLE 26 - INDIRECT ACCESS ADDRESS REGISTER
(DIRECT ACCESSED SPACE) AT 0x34 to 0x35
Field
Bits
Length
ADDRESS[7:0]
7:0
8
ADDRESS[15:8]
15:8
8
Function
Indirect Low Address Register 0x34
Indirect High Address Register 0x35
TABLE 27 - INDIRECT ACCESS CONTROL REGISTER
(DIRECT ACCESSED SPACE) AT 0x3F
Field
Bits
Length
ERROR code
5:0
6
R/WN
6
1
IND_BUSY
7
1
The fields for this register are defined below.
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| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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