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參數(shù)資料
| 型號： | IDT88P8344 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPI交換4 ×的SPI - 3至SPI - 4期1.0 |
| 文件頁數(shù)： | 72/98頁 |
| 文件大?。?/td> | 601K |
| 代理商： | IDT88P8344 |
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IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
The SPI-4 ingress diagnostics register is addressed fromBlock_base
0x0300 + Register_offset 0x0F. The SPI-4 ingress diagnostics register has
diagnostics to force continuous training on the SPI-4 ingress status interface,
insert a DIP-2 error on the SPI-4 ingress status interface, and read the number
of DIP-2 errors seen on the SPI-4 egress status interface.
I_FORCE_TRAIN
ous training on the SPI-4 ingress status interface.
0=Normal status channel operation
1=Force continuous training on the SPI-4 ingress status interface
The I_FORCE_TRAIN field is used to force continu-
I_ERR_INS
2 errors on the SPI-4 ingress status interface programmed into the I_DIP_NUM
field. After the DIP-2 errors are inserted, the I_ERR_INS field will clear itself.
0=Normal status channel operation
1= Insert DIP-2 errors on the SPI-4 ingress status interface
The I_ERR_INS field is used to insert the number of DIP-
I_DIP_NUM
The I_DIP_NUMfield is used to create the number of DIP-2 errors
programmed into the I_DIP_NUMfield on the SPI-4 egress status interface..
SPI-4 ingress DIP-4 error counter (Block_base
0x0300 + Register_offset 0x10)
TABLE 98 - SPI-4 INGRESS DIP-4 ERROR
COUNTER (REGISTER_OFFSET 0x10)
Field
Bits
DIP_4
15:0
SPI-4 ingress start up training threshold register
(Block_base 0x0300 + Register_offset 0x12)
TABLE 100 - SPI-4 INGRESS START UP TRAINING
THRESHOLD REGISTER (REGISTER_OFFSET 0x12)
Field
Bits
STRT_TRAIN
7:0
The SPI-4 ingress start up training threshold register is addressed from
Block_base 0x0300 + Register_offset 0x12. The SPI-4 ingress start up training
threshold register has read and write access. The SPI-4 ingress start up training
threshold register is used to set the number of consecutive training patterns that
will lead to OUT_OF_SYNCH on the SPI-4 ingress data. If the STRT_TRAIN
field is set to zero, then the OUT_OF_SYNCH feature is disabled.
STRT_TRAIN
The STRT_TRAIN field is used to set the number of
consecutive training patterns that will lead to OUT_OF_SYNCH on the SPI-4
ingress data interface.
Length
16
Initial Value
0
The SPI-4 ingress DIP-4 error counter is addressed fromBlock_base
0x0300 + Register_offset 0x10. The SPI-4 ingress DIP-4 error counter has
read access, and automatically clears itself after a read. The SPI-4 ingress DIP-
4 error counter is used in port diagnostics to verify the integrity of the SPI-4
ingress data path.
DIP_4
The DIP_4 field is used to read the number of DIP-4 errors seen on
the SPI-4 egress status interface. The DIP_4 field saturates at the value
0xFFFF, and is automatically cleared after reading to re-start DIP-4 error
counter accumulation.
SPI-4 ingress bit alignment control register
(Block_base 0x0300 + Register_offset 0x11)
TABLE 99 - SPI-4 INGRESS BIT ALIGNMENT
CONTROL REGISTER (REGISTER_OFFSET 0x11)
Field
Bits
FORCE
0
The SPI-4 ingress bit alignment control register is addressed fromBlock_base
0x0300 + Register_offset 0x11. The SPI-4 ingress bit alignment control register
has read and write access. The SPI-4 ingress bit alignment control register is
used to overrule the automatically selected bit phase alignments and go to
manual mode. In manual mode, the PHASE_ASSIGN field [Block_base 0x0800
+ Register_offset 0x0c – 0x1F] now defines the selected phase.
Length
1
Initial Value
0
FORCE
The FORCE field is used to manually align the SPI-4 ingress data.
0=Normal bit alignment operation
1= Force to manual bit alignment mode on SPI-4 ingress data using
the PHASE_ASSIGN field.
Length
8
Initial Value
0
TABLE 101 - SPI-4 EGRESS LID TO LP MAP
(256 ENTRIES)
Field
Bits
LP
EN
There are 256 entries in the SPI-4 egress LID to LP map for the SPI-4 egress
interface. The entries are at Block_base 0x0400 + LID. For example, LID 0x00
is at Block_base 0x0400 + 0x00. A SPI-4 egress LID to LP map has read and
write access. A SPI-4 egress LID to LP map is used to map a logical identifier
used internally to a SPI-4 egress logical port.
0x00 - 0x3F of the LID map is for Module A LIDs 0x00 - 0x3F
0x40 - 0x7F of the LID map is for Module B LIDs 0x00 - 0x3F
0x80 - 0xBF of the LID map is for Module C LIDs 0x00 - 0x3F
0xC0 - 0xFF of the LID map is for Module D LIDs 0x00 - 0x3F
Data for an inactive LP having an entry in the calendar is forwarded to
LID0. Therefore all the LPs that have entries in the calendar tables should be
enabled.
Length
8
1
Initial Value
0x00
0b0
7:0
8
LP
The LP programmed is associated to the LID with the same number as
the register address. Eight bits support the 256 possible LPs on the SPI-4
physical interface. 256 simultaneously active LPs are supported by the
IDT88P8344 device.
EN
The EN bit is used to enable or disable the connection of a LID to an LP.
0=LP is disabled
1=LP is enabled
9.4.6 Common module block base 0x0500 registers
SPI-4 egress calendar_0 (Block_base 0x0500)
TABLE 102 - SPI-4 EGRESS CALENDAR_0
(256 LOCATIONS)
Field
Bits
LP
7:0
The SPI-4 egress calendar_0 is at Block_base 0x0500 and has read and
write access. When the SPI-4 egress calendar_0 is selected, calendar_0 is
in use. There are 256 entries in the SPI-4 egress calendar_0 to schedule the
Length
8
Initial Value
0xFF
9.4.5 Common module block base 0x0400 registers
SPI-4 egress LID to LP map (Block_base 0x0400)
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