參數(shù)資料
型號(hào)： IDT88P8344
廠(chǎng)商： Integrated Device Technology, Inc.
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPI交換4 ×的SPI - 3至SPI - 4期1.0
文件頁(yè)數(shù)： 17/98頁(yè)
文件大?。?/td> 601K
代理商： IDT88P8344
17
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
3.2 SPI-4
Refer to OIF SPI-4 document (see Glossary) for full details of the implemen-
tation agreement.
- Clock rate is 80 - 400 MHz (160 - 800MHz DDR)
- Link and PHY modes supported
- Address range 0 to 255 with support for 256 simultaneously active logical
ports
- MAXBURST parameters configurable 16-256 bytes in 16 byte multiples
- 256 entry calendar
- LVTTL and LVDS status signals supported
The following are implemented for the SPI-4 interface:
- Link / PHY layer device
- Physical port active
3.2.1 SPI-4 ingress
The SPI-4 ingress includes
Bit alignment
Word alignment/ de-skew
Transfer decode and dispatch
PFP interface
Status frame generation
SPI-4 ingress configurable parameters
SPI-4 LID map
- 256 entries, one per SPI-4 LP
- SPI-3 physical interface identifier
- Physical port enable
Word / bit synchronization
- LVDS clock data alignment and LVDS data de-skew
Minimum packet length
- Packets shorter than the mnimumlength will be optionally counted in the
short packet counter.
- Range 0 – 255 in 1 byte increments
Maximum packet length
- Packets longer than the maximumlength will be optionally counted in the
long packet counter.
- Range 0 – 16,383 in 1 byte increments
Free segment backpressure threshold
- Number of free buffer segments allocated to trigger backpressure for the LP
相關(guān)PDF資料
PDF描述
IDT88P8344BHGI SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
IDTAMB0480 ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM MODULES
IDTCSP2510DPGI 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
IDTCSP2510DPG SENSOR OPTICAL SLOTTED 1.0MM
IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
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