參數(shù)資料
型號： LMK04000BEVALXO
廠商： National Semiconductor
文件頁數(shù)： 25/65頁
文件大?。?/td> 0K
描述： BOARD EVAL PREC CLOCK PLL XO
標(biāo)準(zhǔn)包裝： 1
系列： PowerWise®
主要目的： 計(jì)時(shí)，時(shí)鐘調(diào)節(jié)器
嵌入式： 否
已用 IC / 零件： LMK04000
主要屬性： 122.88 MHz 晶體
次要屬性： 集成式 PLL 和 VCO
已供物品： 板，線纜
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Default Device Register Settings After Power On/Reset
Table 4 illustrates the default register settings programmed in silicon for the LMK040xx after power on or
asserting the reset bit.
Table 4. Default Device Register Settings after Power On/Reset
Field Name
Default
Default State
Field Description
Register
Bit Location
Value
(MSB:LSB)
(decimal)
CLKoutX_PECL_LVL
0
2VPECL disabled
This bit sets LVPECL clock level. Valid when
R0 to R4
23
the clock channel is configured as
LVPECL/2VPECL; otherwise, not relevant.
CLKoutXB_STATE
0
Inverted
This field sets the state of output B of an
R1 to R3
22:21
LVCMOS Clock channel.
CLKoutXA_STATE
1
Non-Inverted
This field sets the state of output A of an
R1 to R3
20:19
LVCMOS Clock channel.
EN_CLKoutX
0
OFF
Clock Channel enable bit. Note: The state of
R0 to R4
16
CLKout2 is ON by default.
Reserved Registers
(1)
R5,R6,R8
NA
R9,R10
RC_DLD1_Start
1
Enabled
Forces the VCO tuning algorithm state
R10
29
machine to wait until PLL1 is locked.
CLKin1_BUFTYPE
1
MOS mode
CLKin1 Input Buffer Type
R11
11
CLKin0_BUFTYPE
1
MOS mode
CLKin0 Input Buffer Type
R11
10
LOS_TIMEOUT
1
3 MHz (min.)
Selects Lower Reference Clock input
R11
9:8
frequency for LOS Detection.
LOS_TYPE
3
CMOS
Selects LOS output type (2)
R11
7:6
CLKin_SEL
0
CLKin0
Selects Reference Clock source
R11
5:4
PLL1 CP Polarity
1
Positive polarity
Selects the charge pump output polarity, i.e.,
R12
31
the tuning slope of the external VCXO
PLL1_CP_GAIN
6
100 A
Sets the PLL1 Charge Pump Gain
R12
30:28
PLL1_R Counter
1
Divide = 1
Sets divide value for PLL1_R Counter
R12
27:16
PLL1_N Counter
1
Divide = 1
Sets divide value for PLL1_N Counter
R12
15:4
EN_PLL2_REF2X
0
Disabled
Enables or disables the OSCin frequency
R13
16
doubler path for the PLL2 reference input
EN_PLL2_XTAL
0
OFF
Enables or Disables internal circuits that
R13
21
support an external crystal driving the OSCin
pins
EN_Fout
0
OFF
Enables or disables the VCO output buffer
R13
20
CLK Global Enable
1
Enabled
Global enable or disable for output clocks
R13
18
POWER DOWN
0
Disabled (device is Device power down control
R13
17
active)
PLL2 CP TRI-STATE
0
TRI-STATE
Enables or disables TRI-STATE for PLL2
R13
15
disabled
Charge Pump
PLL1 CP TRI-STATE
0
TRI-STATE
Enables or disables TRI-STATE for PLL1
R13
14
disabled
Charge Pump
OSCin_FREQ
200
200 MHz
Source frequency driving OSCin port
R14
28:21
PLL_MUX
31
Reserved
Selects output routed to LD pin
R14
20:16
PLL2_R Counter
1
Divide = 1
Sets Divide value for PLL2_R Counter
R14
15:4
PLL2_CP_GAIN
2
1600 A
Sets PLL2 Charge Pump Gain
R15
27:26
VCO_DIV
2
Divide = 2
Sets divide value for VCO output divider
R15
25:22
PLL2_N Counter
1
Divide = 1
Sets PLL2_N Counter value
R15
21:4
(1)
These registers are reserved. The Power On/Reset values for these registers are shown in the register map and should not be changed
during programming.
(2)
If the CLKin_SEL value is set to either [0,0] or [0,1], the LOS_TYPE field should be set to [0,0].
Copyright 2008–2011, Texas Instruments Incorporated
31
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