參數(shù)資料
型號(hào)： LMK04000BEVALXO
廠商： National Semiconductor
文件頁(yè)數(shù)： 49/65頁(yè)
文件大小： 0K
描述： BOARD EVAL PREC CLOCK PLL XO
標(biāo)準(zhǔn)包裝： 1
系列： PowerWise®
主要目的： 計(jì)時(shí)，時(shí)鐘調(diào)節(jié)器
嵌入式： 否
已用 IC / 零件： LMK04000
主要屬性： 122.88 MHz 晶體
次要屬性： 集成式 PLL 和 VCO
已供物品： 板，線纜
CLKoutX
CLKoutX*
1
2
0
:
1
2
0
:
0.1 PF
LVPECL
Receiver
100: Trace
(Differential)
LVPECL
Driver
8
2
:
1
2
0
:
Vcc
8
2
:
1
2
0
:
Vcc
0.1 PF
LVDS
Receiver
100: Trace
(Differential)
LVDS
Driver
1
0
:
CLKoutX
CLKoutX*
0.1 PF
LVDS
Receiver
5
0
:
100: Trace
(Differential)
LVDS
Driver
5
0
:
Vbias
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Termination for AC Coupled Differential Operation
AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver
standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is important
to ensure the receiver is biased to its ideal DC level.
When driving non-biased LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC
blocking capacitors, however the proper DC bias point needs to be established at the receiver. One way to do
this is with the termination circuitry in Figure 21.
Figure 21. Differential LVDS Operation, AC Coupling, External Biasing at the Receiver
Some LVDS receivers may have internal biasing on the inputs. In this case, the circuit shown in Figure 21 is
modified by replacing the 50
Ω terminations to Vbias with a single 100 Ω resistor across the input pins of the
receiver, as shown in Figure 22. When using AC coupling with LVDS outputs, there may be a startup delay
observed in the clock output due to capacitor charging. The previous figures employ a 0.1 F capacitor. This
value may need to be adjusted to meet the startup requirements for a particular application.
Figure 22. LVDS Termination for a Self-Biased Receiver
LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120
Ω emitter resistors
close to the LVPECL driver to provide a DC path to ground as shown in Figure 23. For proper receiver operation,
the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical
DC bias voltage for LVPECL receivers is 2 V. A Thevenin equivalent circuit (82
Ω resistor connected to VCC and
a 120
Ω resistor connected to ground with the driver connected to the junction of the 82 Ω and 120 Ω resistors) is
a valid termination as shown in Figure 23 for VCC = 3.3 V. Note this Thevenin circuit is different from the DC
coupled example in Figure 20.
Figure 23. Differential LVPECL Operation, AC Coupling, Thevenin Equivalent, External Biasing at the
Receiver
Copyright 2008–2011, Texas Instruments Incorporated
53
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