參數(shù)資料
型號： LMK04000BEVALXO
廠商： National Semiconductor
文件頁數(shù)： 63/65頁
文件大?。?/td> 0K
描述： BOARD EVAL PREC CLOCK PLL XO
標(biāo)準(zhǔn)包裝： 1
系列： PowerWise®
主要目的： 計時，時鐘調(diào)節(jié)器
嵌入式： 否
已用 IC / 零件： LMK04000
主要屬性： 122.88 MHz 晶體
次要屬性： 集成式 PLL 和 VCO
已供物品： 板，線纜
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V
≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Slew Rate on CLKin
SLEWCLKin
20% to 80%
0.15
0.5
V/ns
(4)
AC coupled to CLKinX;
Input Voltage Swing,
CLKinX* AC coupled to Ground
0.25
2.0
Vpp
single-ended input
(CLKinX_TYPE=0)
VCLKin (Bipolar input buffer
mode)
CLKinX and CLKinX* are both
Input Voltage Swing,
driven, AC coupled.
0.5
3.1
Vpp
differential input
(CLKinX_TYPE=0)
DC offset voltage between
VCLKin-offset (Bipolar input
Each pin AC coupled
CLKinX/CLKinX*
44
mV
buffer mode)
(CLKinX_TYPE=0)
|CLKinX-CLKinX*|
AC coupled to CLKinX;
Input Voltage Swing, single-
CLKinX* AC coupled to Ground
0.25
2.0
Vpp
ended input
(CLKinX_TYPE=1)
VCLKin (MOS input buffer
mode)
CLKinX and CLKinX* are both
Input Voltage Swing,
driven, AC coupled.
0.5
3.1
Vpp
differential input
(CLKinX_TYPE=1)
DC coupled to CLKinX;
VCLKin-VIH (MOS input buffer
Maximum input voltage
CLKinX* AC coupled to Ground
2.0
VCC
V
mode)
(CLKinX_TYPE=1)
DC coupled to CLKinX;
VCLKin-VIL (MOS input buffer
CLKinX* AC coupled to Ground
0.0
0.4
V
mode)
(CLKinX_TYPE=1)
DC offset voltage between
VCLKin-offset (MOS input
Each pin AC coupled
CLKinX/CLKinX*
294
mV
buffer mode)
(CLKinX_TYPE=1)
|CLKinX-CLKinX*|
PLL1 Specifications
PLL1 Phase Detector
fPD
40
MHz
Frequency
VCPout1 = VCC/2,
25
PLL1_CP_GAIN = 100b
VCPout1 = VCC/2,
50
PLL1_CP_GAIN = 101b
VCPout1 = VCC/2,
100
PLL1_CP_GAIN = 110b
VCPout1 = VCC/2,
PLL1 Charge Pump Source
400
ICPout1 SOURCE
A
PLL1_CP_GAIN = 111b
Current (5)
PLL1_CP_GAIN = 000b
NA
PLL1_CP_GAIN = 001b
NA
VCPout1=VCC/2, PLL1_CP_GAIN
20
= 010b
VCPout1=VCC/2, PLL1_CP_GAIN
80
= 011b
(4)
In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all
input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input
slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended
clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to
their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to
achieve optimal phase noise performance at the device outputs.
(5)
This parameter is programmable
Copyright 2008–2011, Texas Instruments Incorporated
7
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