- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16185 > LMK04000BEVALXO (National Semiconductor)BOARD EVAL PREC CLOCK PLL XO PDF資料下載
參數(shù)資料
| 型號： | LMK04000BEVALXO |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 31/65頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL PREC CLOCK PLL XO |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PowerWise® |
| 主要目的： | 計時，時鐘調(diào)節(jié)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LMK04000 |
| 主要屬性： | 122.88 MHz 晶體 |
| 次要屬性： | 集成式 PLL 和 VCO |
| 已供物品： | 板，線纜 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
PLL1_R: PLL1_R Counter
The size of the PLL1_R counter is 12 bits. This counter will support a maximum divide ratio of 4095 and
minimum divide ratio of 1.
Table 17. PLL1_R Counter Values
R [11:0]
VALUE
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
Not Valid
0
1
.
...
1
4095
PLL1 Charge Pump Current Gain (PLL1_CP_GAIN) and Polarity Control (PLL1_CP_POL)
The Loop Band Width (LBW) on PLL1 should be narrow to suppress the noise from the system or input clocks at
CLKinX/CLKinX* port. This configuration allows the noise of the external VCXO to dominate at low offset
frequencies. Given that the noise of the external VCXO is far superior than the noise of PLL1, this setting
produces a very clean reference clock to PLL2 at the OSCin port.
In order to achieve a LBW as low as 10 Hz at the supported VCXO frequency (1 MHz to 200 MHz), a range of
charge pump currents in PLL1 is provided. The table below shows the available current gains. A small charge
pump current is required to obtain a narrow LBW at high phase detector rate (small N value).
Table 18. PLL1 Charge Pump Current Selections (PLL1_CP_GAIN)
PLL1_CP_GAIN [2:0]
PLL1 Charge Pump Current Magnitude (A)
b2
b1
b0
0
RESERVED
0
1
RESERVED
0
1
0
20
0
1
80
1
0
25
1
0
1
50
1
0
100
1
400
The PLL1_CP_POL bit sets the PLL1 charge pump for operation with a positive or negative slope VCO/VCXO. A
positive slope VCO/VCXO increases frequency with increased tuning voltage. A negative slope VCO/VCXO
increases frequency with decreased tuning voltage.
Table 19. PLL1 Charge Pump Polarity Control Bits (PLL1_CP_POL)
PLL1_CP_POL
DESCRIPTION
0
Negative Slope VCO/VCXO
1
Positive Slope VCO/VCXO
Register 13
EN_PLL2_XTAL: Crystal Oscillator Option Enable
If an external crystal is being used to implement a discrete VCXO, the internal feedback amplifier must be
enabled in order to complete the oscillator circuit.
Copyright 2008–2011, Texas Instruments Incorporated
37
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 380LX822M063A032 | CAP ALUM 8200UF 63V 20% SNAP |
| A3CKB-3036M | IDC CABLE - AKC30B/AE30M/APK30B |
| 381LX391M400A042 | CAP ALUM 390UF 400V 20% SNAP |
| ECM06DTMN-S664 | CONN EDGECARD 12POS R/A .156 |
| M3UYK-2606J | IDC CABLE - MKS26K/MC26G/MPD26K |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMK04000BISQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
| LMK04000BISQ/NOPB | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LMK04000BISQE | 制造商:Texas Instruments 功能描述:Clock Conditioner 48-Pin LLP EP T/R |
| LMK04000BISQE/NOPB | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LMK04000BISQX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。