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參數(shù)資料
| 型號(hào)： | LMK04000BEVALXO |
| 廠商： | National Semiconductor |
| 文件頁(yè)數(shù)： | 48/65頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL PREC CLOCK PLL XO |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PowerWise® |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘調(diào)節(jié)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LMK04000 |
| 主要屬性： | 122.88 MHz 晶體 |
| 次要屬性： | 集成式 PLL 和 VCO |
| 已供物品： | 板，線纜 |
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CLKoutX
CLKoutX*
LVPECL
Receiver
1
2
0:
100: Trace
(Differential)
1
2
0:
Vcc
LVPECL
Driver
8
2:
8
2:
CLKoutX
CLKoutX*
LVPECL
Receiver
5
0:
100: Trace
(Differential)
5
0:
Vcc - 2 V
LVPECL
Driver
CLKoutX
CLKoutX*
LVDS
Receiver
1
0
0:
100: Trace
(Differential)
LVDS
Driver
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
It is possible to drive a non-LVPECL or non-LVDS receiver with an LVDS or LVPECL driver as long as the above
guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best
termination and coupling method to be sure that the receiver is biased at its optimum DC voltage (common mode
voltage). For example, when driving the OSCin/OSCin* input of the LMK04000 family, OSCin/OSCin* should be
AC coupled because OSCin/OSCin* biases the signal to the proper DC level (See Figure 13) This is only slightly
different from the AC coupled cases described in Driving CLKin Pins with a Single-Ended Source because the
DC blocking capacitors are placed between the termination and the OSCin/OSCin* pins, but the concept remains
the same. The receiver (OSCin/OSCin*) sets the input to the optimum DC bias voltage (common mode voltage),
not the driver.
Termination for DC Coupled Differential Operation
For DC coupled operation of an LVDS driver, terminate with 100
Ω as close as possible to the LVDS receiver as
shown in Figure 18.
Figure 18. Differential LVDS Operation, DC Coupling, No Biasing of the Receiver
For DC coupled operation of an LVPECL driver, terminate with 50
Alternatively terminate with a Thevenin equivalent circuit (120
Ω resistor connected to VCC and an 82 Ω resistor
connected to ground with the driver connected to the junction of the 120
Ω and 82 Ω resistors) as shown in
Figure 19. Differential LVPECL Operation, DC Coupling
Figure 20. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent
52
Copyright 2008–2011, Texas Instruments Incorporated
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