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參數(shù)資料
| 型號(hào)： | LMK04000BEVALXO |
| 廠商： | National Semiconductor |
| 文件頁(yè)數(shù)： | 52/65頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL PREC CLOCK PLL XO |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PowerWise® |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘調(diào)節(jié)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LMK04000 |
| 主要屬性： | 122.88 MHz 晶體 |
| 次要屬性： | 集成式 PLL 和 VCO |
| 已供物品： | 板，線纜 |
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0.1 PF
50: Trace
5
0
:
LMK040XX
Clock Source
CLKinX
CLKinX*
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Figure 30. CLKinX/X* Single-ended Termination
If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or AC
coupling may be used. If DC coupling is used, the CLKinX_TYPE should be set to MOS buffer mode
(CLKinX_TYPE = 1) and the voltage swing of the source must meet the specifications for DC coupled, MOS-
mode clock inputs given in the table of Electrical Characteristics. If AC coupling is used, the CLKinX_TYPE
should be set to the bipolar buffer mode (CLKinX_TYPE = 0). The voltage swing at the input pins must meet the
specifications for AC coupled, bipolar mode clock inputs given in the table of Electrical Characteristics. In this
case, some attenuation of the clock input level may be required. A simple resistive divider circuit before the AC
coupling capacitor is sufficient.
Figure 31. DC Coupled LVCMOS/LVTTL Reference Clock
Additional Outputs with an LMK04000 Family Device
The number of outputs on a LMK04000 family device can be expanded in many ways. The first method is to use
the differential outputs as two single-ended outputs. For CMOS outputs, both the positive and negative outputs
can be programmed to be in phase, or 180 degrees out of phase. LVDS/LVPECL positive and negative outputs
are always 180 degrees out of phase. LVDS single-ended is not recommended.
In addition to this technique, the number of outputs can be expanded with a LMK01000 family device. To do this,
one of the clock outputs of a LMK04000 can drive the LMK01000 device.
For more information on phase synchronization with multiple devices, please refer to application note AN-1864:
Output Clock Phase Noise Performance VS. VCXO Phase Noise
The jitter cleaning capability of the LMK04000 family is highly dependent on the phase noise performance of the
VCXO (or crystal) that is integrated with PLL1. The VCXO is the reference for PLL2 which provides the clock for
the output distribution path. Consequently, the designer must choose a VCXO (or crystal) that supports the
required performance at the clock outputs.
An example of the difference in performance that can be obtained from various VCXOs is illustrated in the
following plots. Figure 32 compares the phase noise of two different VCXOs: VCXO “A” and VCXO “B”. Both
VCXOs have a center frequency of 100 MHz. The figure of merit, RMS jitter, is measured over the bandwidth
100 Hz to 200 kHz. This is the most relevant integration bandwidth for the VCXO because it will have the most
impact inside the loop bandwidth of PLL2.
56
Copyright 2008–2011, Texas Instruments Incorporated
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