參數(shù)資料
型號: LMK04000BEVALXO
廠商: National Semiconductor
文件頁數(shù): 33/65頁
文件大小: 0K
描述: BOARD EVAL PREC CLOCK PLL XO
標準包裝: 1
系列: PowerWise®
主要目的: 計時,時鐘調(diào)節(jié)器
嵌入式:
已用 IC / 零件: LMK04000
主要屬性: 122.88 MHz 晶體
次要屬性: 集成式 PLL 和 VCO
已供物品: 板,線纜
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Table 23. PLL2 Internal Loop Filter Resistor Values, PLL2_R4_LF
PLL2_R4_LF [2:0]
RESISTANCE
b2
b1
b0
0
< 200
Ω
0
1
10 k
Ω
0
1
0
20 k
Ω
0
1
30 k
Ω
1
0
40 k
Ω
1
0
1
Invalid
1
0
Invalid
1
Invalid
Internal loop filter capacitors for C3 and C4 can be set individually according to the following table.
Table 24. PLL2 Internal Loop Filter Capacitor Values
PLL2_C3_C4_LF [3:0]
Loop Filter Capacitance(pF)
b3
b2
b1
b0
0
C3 = 0, C4 = 10
0
1
C3 = 0, C4 = 60
0
1
0
C3 = 50, C4 = 10
0
1
C3 = 0, C4 = 110
0
1
0
C3 = 50, C4 = 110
0
1
0
1
C3 = 100, C4 = 110
0
1
0
C3 = 0, C4 = 160
0
1
C3 = 50, C4 = 160
1
0
C3 = 100, C4 = 10
1
0
1
C3 = 100, C4 = 60
1
0
1
0
C3 = 150, C4 = 110
1
0
1
C3 = 150, C4 = 60
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Reserved
PLL1 CP TRI-STATE and PLL2 CP TRI-STATE
The charge pump output of either CPout1 or CPout2 may be placed in a TRI-STATE mode by setting the
appropriate PLLx CP TRI-STATE bit.
Table 25. PLL1 Charge Pump TRI-STATE bit values
PLL1 CP TRI-STATE
Description
1
PLL1 CPout1 is at TRI-STATE
0
PLL1 CPout1 is active
Table 26. PLL2 Charge Pump TRI-STATE bit values
PLL2 CP TRI-STATE
Description
1
PLL2 CPout2 is at TRI-STATE
0
PLL2 CPout2 is active
Copyright 2008–2011, Texas Instruments Incorporated
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