參數(shù)資料
型號(hào): M58WR128EBZB
廠商: 意法半導(dǎo)體
英文描述: 128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory
中文描述: 128兆位和8Mb × 16,多銀行,突發(fā)1.8V電源快閃記憶體
文件頁(yè)數(shù): 17/87頁(yè)
文件大?。?/td> 1113K
代理商: M58WR128EBZB
24/87
or Erase operation. Indeterminate results can oc-
cur if VPP becomes invalid during an operation.
When the VPP Status bit is Low (set to ‘0’), the volt-
age on the VPP pin was sampled at a valid voltage;
when the VPP Status bit is High (set to ‘1’), the VPP
pin has a voltage that is below the VPP Lockout
Voltage, VPPLK, the memory is protected and Pro-
gram and Erase operations cannot be performed.
Once set High, the VPP Status bit can only be reset
Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Suspend Status Bit (SR2). The
Pro-
gram Suspend Status bit indicates that a Program
operation has been suspended in the addressed
block. When the Program Suspend Status bit is
High (set to ‘1’), a Program/Erase Suspend com-
mand has been issued and the memory is waiting
for a Program/Erase Resume command. The Pro-
gram Suspend Status should only be considered
valid when the Program/Erase Controller Status
bit is High (Program/Erase Controller inactive).
SR2 is set within the Program Suspend Latency
time of the Program/Erase Suspend command be-
ing issued therefore the memory may still com-
plete the operation rather than entering the
Suspend mode.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Block Protection Status Bit (SR1). The
Block
Protection Status bit can be used to identify if a
Program or Block Erase operation has tried to
modify the contents of a locked block.
When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been at-
tempted on a locked block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the new command will appear to fail.
Bank Write/Multiple Word Program Status Bit
(SR0). The Bank Write Status bit indicates wheth-
er the addressed bank is programming or erasing.
In Enhanced Factory Program mode the Multiple
Word Program bit shows if a Word has finished
programming or verifying depending on the phase.
The Bank Write Status bit should only be consid-
ered valid when the Program/Erase Controller Sta-
tus SR7 is Low (set to ‘0’).
When both the Program/Erase Controller Status bit
and the Bank Write Status bit are Low (set to ‘0’),
the addressed bank is executing a Program or
Erase operation. When the Program/Erase Con-
troller Status bit is Low (set to ‘0’) and the Bank
Write Status bit is High (set to ‘1’), a Program or
Erase operation is being executed in a bank other
than the one being addressed.
In Enhanced Factory Program mode if Multiple
Word Program Status bit is Low (set to ‘0’), the de-
vice is ready for the next Word, if the Multiple Word
Program Status bit is High (set to ‘1’) the device is
not ready for the next Word.
Note: Refer to Appendix C, Flowcharts and Pseu-
do Codes, for using the Status Register.
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