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參數(shù)資料
| 型號： | M58WR128EBZB |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
| 中文描述： | 128兆位和8Mb × 16，多銀行，突發(fā)1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 63/87頁 |
| 文件大?。?/td> | 1113K |
| 代理商： | M58WR128EBZB |
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Table 39. Protection Register Information
Table 40. Burst Read Information
Table 41. Bank and Erase Block Region Information
Note: 1. The variable P is a pointer which is defined at CFI offset 15h.
2. Bank Regions. There are two Bank Regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks
that are made up of the parameter and main blocks.
Offset
Data
Description
Value
(P+E)h = 47h
0001h
Number of protection register fields in JEDEC ID space. 0000h indicates that
256 fields are available.
1
(P+F)h = 48h
0080h
Protection Field 1: Protection Description
Bits 0-7 Lower byte of protection register address
Bits 8-15 Upper byte of protection register address
Bits 16-23 2n bytes in factory pre-programmed region
Bits 24-31 2n bytes in user programmable region
0080h
(P+10)h = 49h
0000h
(P+11)h = 4Ah
0003h
8 Bytes
(P+12)h= 4Bh
0004h
16 Bytes
Offset
Data
Description
Value
(P+13)h = 4Ch
0003h
Page-mode read capability
bits 0-7
’n’ such that 2n HEX value represents the number of read-
page bytes. See offset 28h for device word width to
determine page-mode data output width.
8 Bytes
(P+14)h = 4Dh
0004h
Number of synchronous mode read configuration fields that follow.
4
(P+15)h = 4Eh
0001h
Synchronous mode read capability configuration 1
bit 3-7
Reserved
bit 0-2
’n’ such that 2n+1 HEX value represents the maximum
number of continuous synchronous reads when the device is
configured for its maximum word width. A value of 07h
indicates that the device is capable of continuous linear bursts
that will output data until the internal burst counter reaches
the end of the device’s burstable address space. This field’s
3-bit value can be written directly to the read configuration
register bit 0-2 if the device is configured for its maximum
word width. See offset 28h for word width to determine the
burst data output width.
4
(P+16)h = 4Fh
0002h
Synchronous mode read capability configuration 2
8
(P+17)h = 50h
0003h
Synchronous mode read capability configuration 3
16
(P+18)h =51h
0007h
Synchronous mode read capability configuration 4
Cont.
M58WR128ET (top)
M58WR128EB (bottom)
Description
Offset
Data
Offset
Data
(P+19)h = 52h
02h
(P+19)h = 52h
02h
Number of Bank Regions within the device
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58WR128ET | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
| M58WR128ET10ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
| M58WR128ET70ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
| M58WR128ET80ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
| M58WR128ETZB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
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