參數(shù)資料
型號: M58WR128EBZB
廠商: 意法半導體
英文描述: 128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory
中文描述: 128兆位和8Mb × 16,多銀行,突發(fā)1.8V電源快閃記憶體
文件頁數(shù): 20/87頁
文件大?。?/td> 1113K
代理商: M58WR128EBZB
27/87
(no wrap). The Wrap Burst bit is used to select be-
tween wrap and no wrap. When the Wrap Burst bit
is set to ‘0’ the burst read wraps; when it is set to
‘1’ the burst read does not wrap.
Burst length Bits (CR2-CR0)
The Burst Length bits set the number of Words to
be output during a Synchronous Burst Read oper-
ation as result of a single address latch cycle.
They can be set for 4 words, 8 words, 16 words or
continuous burst, where all the words are read se-
quentially.
In continuous burst mode the burst sequence can
cross bank boundaries.
In continuous burst mode, in 4, 8 words no-wrap,
or in 16 words, depending on the starting address,
the device asserts the WAIT output to indicate that
a delay is necessary before the data is output.
If the starting address is aligned to a 4 word
boundary no wait states are needed and the WAIT
output is not asserted.
If the starting address is shifted by 1, 2 or 3 posi-
tions from the four word boundary, WAIT will be
asserted for 1, 2 or 3 clock cycles when the burst
sequence crosses the first 64 word boundary, or
the 16 word boundary in the case of 16-word wrap
burst, to indicate that the device needs an internal
delay to read the successive words in the array.
WAIT will be asserted only once during a continu-
ous burst access. See also Table 10, Burst Type
Definition.
CR14, CR5 and CR4 are reserved for future use.
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