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參數(shù)資料
| 型號： | M58WR128EBZB |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
| 中文描述： | 128兆位和8Mb × 16，多銀行，突發(fā)1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 27/87頁 |
| 文件大?。?/td> | 1113K |
| 代理商： | M58WR128EBZB |
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other modes, WAIT is always asserted (except for
Read Array mode).
See Table 21, Synchronous Read AC Character-
istics and Figure 12, Synchronous Burst Read AC
Waveform for details.
Synchronous Burst Read Suspend. A
Syn-
chronous Burst Read operation can be suspend-
ed, freeing the data bus for other higher priority
devices. It can be suspended during the initial ac-
cess latency time (before data is output) in which
case the initial latency time can be reduced to ze-
ro, or after the device has output data. When the
Synchronous Burst Read operation is suspended,
internal array sensing continues and any previous-
ly latched internal data is retained. A burst se-
quence can be suspended and resumed as often
as required as long as the operating conditions of
the device are met.
A Synchronous Burst Read operation is suspend-
ed when E is low and the current address has
been latched (on a Latch Enable rising edge or on
a valid clock edge). The clock signal is then halted
at VIH or at VIL, and G goes high.
When G becomes low again and the clock signal
restarts, the Synchronous Burst Read operation is
resumed exactly where it stopped.
WAIT being gated by E remains active and will not
revert to high-impedance when G goes high. So if
two or more devices are connected to the system’s
READY signal, to prevent bus contention the
WAIT signal of the Flash memory should not be di-
rectly connected to the system’s READY signal.
See Table 21, Synchronous Read AC Character-
istics and Figure 14, Synchronous Burst Read
Suspend AC Waveform for details.
Single Synchronous Read Mode
Single Synchronous Read operations are similar
to Synchronous Burst Read operations except that
only the first data output after the X latency is valid.
Synchronous Single Reads are used to read the
Electronic Signature, Status Register, CFI, Block
Protection Status, Configuration Register Status
or Protection Register. When the addressed bank
is in Read CFI, Read Status Register or Read
Electronic Signature mode, the WAIT signal is al-
ways asserted.
See Table 21, Synchronous Read AC Character-
istics and Figure 12, Single Synchronous Read AC
Waveform for details.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58WR128ET | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
| M58WR128ET10ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
| M58WR128ET70ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
| M58WR128ET80ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
| M58WR128ETZB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
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