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參數(shù)資料
| 型號(hào)： | MC68HC05C0P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 16/96頁 |
| 文件大?。?/td> | 357K |
| 代理商： | MC68HC05C0P |
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MOTOROLA
Section 3: CPU Core
Page 14
MC68HC05C0 Specification Rev. 1.2
3.1.1
ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of
arithmetic calculations or data manipulations.
3.1.2
INDEX REGISTER (X)
The index register is an 8-bit register used for the indexed addressing value to create an
effective address. The index register may also be used as a temporary storage area.
3.1.3
PROGRAM COUNTER (PC)
The program counter is a 16-bit register that contains the address of the next byte to be
fetched.
3.1.4
STACK POINTER (SP)
The stack pointer contains the address of the next free location on the stack. During Reset
or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The
stack pointer is then decremented as data is pushed onto the stack and incremented as
data is pulled from the stack.
When accessing memory, the ten most significant bits are permanently set to 0000000011.
These ten bits are appended to the six least significant register bits to produce an address
within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal)
locations. If 64 locations are exceeded, the stack pointer wraps around and loses the
previously stored information. A subroutine call occupies two locations on the stack; an
interrupt uses five locations.
3.1.5
CONDITION CODE REGISTER (CCR)
The condition code register is a 5-bit register in which four bits are used to indicate the
results of the instruction just executed, and the fifth bit indicates whether interrupts are
masked. These bits can be individually tested by a program, and specific actions can be
taken as a result of their state. Each bit is explained in the following paragraphs.
3.1.5.1
Half Carry (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between
bits 3 and 4.
3.1.5.2
Interrupt (I)
When this bit is set, all interrupts with the exception of SWI are masked (disabled). If a non-
SWI interrupt occurs while this bit is set, the interrupt is latched and processed as soon as
the interrupt bit is cleared. SWI causes an interrupt regardless of the state of this bit.
3.1.5.3
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation
was negative.
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