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參數(shù)資料
| 型號： | MC68HC05C0P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 32/96頁 |
| 文件大?。?/td> | 357K |
| 代理商： | MC68HC05C0P |
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Section 7: Input/Output Ports
MOTOROLA
Page 29
MC68HC05C0 Specification Rev. 1.2
SECTION 7
INPUT/OUTPUT PORTS
The MC68HC05C0 has 18 lines arranged as one 8-bit I/O port (Port D), one 6-bit I/O port
(Port B), and one 4-bit I/O port (Port C). The I/O ports are programmable as either inputs
or outputs under software control of the data direction registers. There is no internal Port
A, although an external port replacement unit may be used.
NOTE:
To avoid a glitch on the output pins, write data to the I/O Port Data
Register before writing a one to the corresponding Data Direction
Register.
7.1
PORT B
Port B is a 6-bit bidirectional port which shares its pins with the 16-Bit Timer subsystem, the
SCI subsystem and CS1. See Section 11 16-BIT TIMER and Section 12, SERIAL
COMMUNICATIONS INTERFACE for a detailed description of these subsystems. See
Section 8.2 CHIP SELECTS for more details on CS1. The address of the Port B data
register is $01 and the data direction register (DDR) is at address $05. Reset does not
affect the data register, but clears the data direction register, thereby returning the ports to
inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. PB0 has
a high current sink and source capability.
7.2
PORT C
Port C is a 4-bit bidirectional port which does not share any of its pins with other
subsystems. The address of the Port C data register is $02 and the data direction register
(DDR) is at address $06. Reset does not affect the data register, but clears the data
direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the
corresponding port bit to output mode. Port C is not available on the 40 pin PDIP package,
and only PC0 and PC2 are available on the 42 pin SDIP package.
7.3
PORT D
Port D is an 8-bit bidirectional port which becomes the lower address byte during Non-
Muxed mode. See Section 9 ADDRESS/DATA BUS INTERFACE for a detailed description.
The address of the Port D data register is $03 and the data direction register (DDR) is at
address $07. Reset does not affect the data register, but clears the data direction register,
thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port
bit to output mode. When Port D cannot be used as general purpose
I/O (Non-Muxed
Mode), addresses $03 and $07 are mapped externally. Port D can also be programmed to
enable internal pullups and generate an interrupt when any of the 8 I/O lines are pulled low.
This requires that the Keyboard Scan is enabled (KSEN) in the External Interrupt Control/
Status Register, and the DDR for any interrupt causing Port D bit is configured as an input.
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