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參數(shù)資料
| 型號： | MC68HC05C0P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 85/96頁 |
| 文件大?。?/td> | 357K |
| 代理商： | MC68HC05C0P |
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Section 12: Serial Communications Interface
MOTOROLA
Page 77
MC68HC05C0 Specification Rev. 1.2
RDRF - Receive Data Register Full Flag
This bit is set when the contents of the receiver serial shift register are transferred to the
receiver data register (SCDAT). The RDRF bit can only be cleared by first accessing the
SCSR with RDRF set, followed by a read of the receiver data register (SCDAT).
If multiple errors are detected in any one received word, the NF, FE, and RDRF bits will be
affected as appropriate during the same clock cycle.
IDLE - Idle Line Detected Flag
This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven
consecutive 1’s). The minimum number of consecutive 1’s needed is 10 (M=0) or 11 (M=1).
This allows a receiver that is not in wake-up mode to detect the end of a message, detect
the preamble of a new message, or to re-synchronize with the transmitter.
The IDLE bit can only be cleared by first accessing the SCSR with IDLE set, followed by a
read of the receiver data register (SCDAT).
Once cleared, IDLE will not be set again until after RDRF has been set (until after the line
has been active and becomes idle again). Also, the IDLE bit will not be set by an idle line
when the receiver wakes up from idle wake-up mode (RWU=1 and WAKE=0).
When the receiver is first enabled, any initial idle or preamble received will not set the IDLE
flag. The IDLE will not be set until after RDRF has been set.
OR - Overrun Error Flag
This bit is set when a new byte is ready to be transferred from the receiver shift register to
the receiver data register (SCDAT) and the receive data register is already full (RDRF bit
is set). Data transfer is then inhibited until this bit is cleared. Data in the receive data
register is valid in this case, but additional data received during an overrun condition
(including the byte causing the overrun) will be lost.
The OR bit can only be cleared by first accessing the SCSR with OR set, followed by a read
of the receiver data register (SCDAT).
NF - Noise Error Flag
This bit is set if there is noise on a “valid” start bit, any of the data bits, or on the stop bit. It
is not set by noise on the idle line nor by invalid start bits. If there is noise, the NF bit is not
set until the RDRF bit is set.
The NF bit represents the status of the byte in the receiver data register (SCDAT). For the
byte being received (shifted in) there will also be a “working” noise flag which will be
transferred to the NF bit when the serial data is loaded into the receive data register. The
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