參數(shù)資料
型號: MC68HC05C0P
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40
封裝: DIP-40
文件頁數(shù): 46/96頁
文件大小: 357K
代理商: MC68HC05C0P
Section 9: Address/Data Bus Interface
MOTOROLA
Page 41
MC68HC05C0 Specification Rev. 1.2
Table 9-3: Non-Muxed Mode Timing
9.4
CLOCK STRETCHED BUS TIMING
If CS1 is configured as a Page-0 chip select type, clock stretching can be enabled to
accommodate slow external peripherals. See Section 8.3.7 CS1P1:CS1P0 - Chip Select 1
Parameters. In either muxed or non-muxed mode, the access/write time, time to float and
data hold time are increased with clock stretching as shown in the timing diagrams below.
In these diagrams, OSC1 is the oscillator clock. The internal bus frequency is a divide-by-
four of the oscillator frequency.
symbol
characteristic
bus time in nanoseconds
min
typ
max
tvarwl
address valid to rd~ or wr~ fall
TBD
3*Tosc/TBD
TBD
trl
rd~ low pulse width
TBD
4*Tosc/TBD
TBD
trdsu
read data setup time to rd~ rise
TBD
10ns/TBD
TBD
trdh
read data hold time after rd~ rise
TBD
0/TBD
TBD
ttf
time to oat for external peripherals
TBD
4*Tosc/TBD
TBD
twl
wr~ low pulse width
TBD
4*Tosc/TBD
TBD
twdsu
write data setup time to wr~ rise
TBD
4*Tosc/TBD
TBD
twdh
write data hold time after wr~ rise
TBD
4*Tosc/TBD
TBD
Tosc is one-half oscillator period
(Bus cycle = 4x oscillator period)
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