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參數(shù)資料
| 型號(hào)： | MC68HC05C0P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁(yè)數(shù)： | 27/96頁(yè) |
| 文件大小： | 357K |
| 代理商： | MC68HC05C0P |
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MOTOROLA
Section 5: Resets
Page 24
MC68HC05C0 Specification Rev. 1.2
5.2
COMPUTER OPERATING PROPERLY (COP) RESET
The MCU contains a watchdog timer that when enabled, automatically times out if not reset
(cleared) within a specific time by a program reset sequence. If the COP watchdog timer is
allowed to time out, a reset is generated to reset the MCU and external peripheral. See
Section 10 MULTI-FUNCTION TIMER, for more information on the COP Watchdog timer.
5.3
LOW-VOLTAGE RESET
The internal low voltage (LVR) reset is generated when the supply voltage to the VDD pin
falls below a nominal 3.50 VDC. The LVR threshold is not intended to be an accurate and
stable trip point, but is intended to assure that the CPU will be held in reset when the VDD
supply voltage is below reasonable operating limits. An enable bit (LVREN) is provided in
the Configuration Register to activate the LVR. If the LVR is not desired, or if the part is
used in a low voltage application, the LVR can be left disabled.
The low voltage reset will be activated as long as the low voltage reset condition exists. This
will also hold the MCU and external peripherals in reset. When the low voltage condition
ends, the low voltage reset will remain active for an additional 4064 cycles. If the LVR is
tripped only for a very short time, the LVR reset signal will still last at least eight processor
clock cycles (tcyc). If any other reset function is active at the end of the LVR reset signal, the
RESET signal will remain low until the other reset condition(s) end.
5.4
ILLEGAL STOP RESET
The Configuration Register provides a one-time writable bit to enable/disable STOP. If
STOP mode is disabled and a STOP instruction is executed, an illegal STOP reset occurs.
This is to protect against runaway code which could inadvertently execute STOP, thereby
preventing a COP time-out to occur.
5.5
RESET PIN
The MCU is reset when a logic zero is applied to the RESET input for a period of one and
one-half machine cycles (t
cyc).
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