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參數(shù)資料
| 型號： | MC68HC05C0P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 60/96頁 |
| 文件大小： | 357K |
| 代理商： | MC68HC05C0P |
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MOTOROLA
Section 11: 16-Bit Timer
Page 54
MC68HC05C0 Specification Rev. 1.2
Figure 11-1: Timer Block Diagram
The counter alternate register differs from the counter register in one respect: a read of the
counter register MSB can clear the timer overflow flag (TOF). Therefore, the counter
alternate register can be read at any time without the possibility of missing timer overflow
interrupts due to clearing of the TOF.
The free-running counter is configured to $FFFC (to facilitate testing TOF) during reset and
is always a read-only register. During a power-on reset, the counter is also preset to $FFFC
and begins running after the oscillator start-up delay. Because the free-running counter is
16 bits preceded by a fixed divided-by-four prescaler, the value in the free-running counter
repeats every 262,144 internal bus clock cycles. When the counter rolls over from $FFFF
to $0000, the TOF bit is set and an interrupt will result if the timer overflow interrupt enable
bit (TOIE) is set.
Input
Capture
Register
Clock
Internal Bus
Output
Compare
Register
High
Byte
Low
Byte
$0E
$0F
/4
Internal
Processor
16-Bit Free
Running
Counter
Alternate
Register
8-Bit
Buffer
High
Byte
Low
Byte
$12
$13
$10
$11
High
Byte
Low
Byte
$0C
$0D
Output
Compare
Circuit
Overflow
Detect
Circuit
Edge
Detect
Circuit
Timer
Status
Reg.
ICF OCF TOF $0B
IEDG OLVL
Output
Level
Reg.
RESET
Timer Control Reg $0A
Output
Level
(TCMP)
Interrupt
Circuit
TOIE
OCIE
Edge
Input
(TCAP)
D
CLK
C
Q
ICIE
OCM ICM
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