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參數(shù)資料
| 型號： | MC68HC05C0P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 86/96頁 |
| 文件大?。?/td> | 357K |
| 代理商： | MC68HC05C0P |
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MOTOROLA
Section 12: Serial Communications Interface
Page 78
MC68HC05C0 Specification Rev. 1.2
NF bit does not generate an interrupt because the RDRF bit gets set with NF and RDRF
can be used to generate the interrupt.
The NF bit can only be cleared by first accessing the SCSR with NF set, followed by a read
of the receive data register (SCDAT).
FE - Framing Error Flag
This bit is set when the word boundaries in the bit stream are not synchronized with the
receiver bit counter (generated by the reception of a logic zero bit where a stop bit was
expected). The received byte is still transferred to the received data register. The FE bit is
not set until the RDRF bit is set.
The FE bit does not generate an interrupt because the RDRF bit gets set with FE and
RDRF can be used to generate the interrupt.
If the received byte causes both a framing error and overrun error, the processor will only
recognize the overrun error. The framing error flag inhibits further transfer of data into the
receive data register (SCDAT) until it is cleared.
The FE bit can only be cleared by first accessing the SCSR with FE set, followed by a read
of the receive data register (SCDAT).
12.6.5
BAUD RATE REGISTER
The Baud Rate Register selects the SCI transmitter and receiver baud rates. All bits are
read/writable.
NOTE:
The Baud Rate Register should not be manipulated while the transmitter
or the receiver is enabled.
Figure 12-13: Serial Communications Baud Rate Register
RD
WR
RST
76543210
SCBR
$14
0
SCR0
SCR1
SCR2
SCP1
SCP0
SCT2
SCT1
SCT0
0
111
1
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