參數(shù)資料
型號: MC68HC05C0P
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40
封裝: DIP-40
文件頁數(shù): 49/96頁
文件大?。?/td> 357K
代理商: MC68HC05C0P
MOTOROLA
Section 9: Address/Data Bus Interface
Page 44
MC68HC05C0 Specification Rev. 1.2
Table 9-4: Clock Stretched Muxed Mode Timing
Table 9-5: Clock Stretched Non-Muxed Mode Timing
symbol
characteristic
bus time in nanoseconds
min
typ
max
tash
address strobe high pulse width
TBD
2*Tosc/TBD
TBD
taddsu
address strobe setup time
TBD
2*Tosc/TBD
TBD
taddh
address strobe hold time
TBD
Tosc/TBD
TBD
tvarwl
address valid to rd~ or wr~ fall
TBD
3*Tosc/TBD
TBD
trl
rd~ low pulse width
TBD
24*Tosc/TBD
TBD
trdsu
read data setup time to rd~ rise
TBD
10ns/TBD
TBD
trdh
read data hold time after rd~ rise
TBD
0/TBD
TBD
ttf
time to float for external peripherals
TBD
5*Tosc/TBD
TBD
twl
wr~ low pulse width
TBD
24*Tosc/TBD
TBD
twdsu
write data setup time to wr~ rise
TBD
24*Tosc/TBD
TBD
twdh
write data hold time after wr~ rise
TBD
5*Tosc/TBD
TBD
Tosc is one-half oscillator period
(Bus cycle = 4x oscillator period)
symbol
characteristic
bus time in nanoseconds
min
typ
max
tvarwl
address valid to rd~ or wr~ fall
TBD
3*Tosc/TBD
TBD
trl
rd~ low pulse width
TBD
24*Tosc/TBD
TBD
trdsu
read data setup time to rd~ rise
TBD
10ns/TBD
TBD
trdh
read data hold time after rd~ rise
TBD
0/TBD
TBD
ttf
time to oat for external peripherals
TBD
8*Tosc/TBD
TBD
twl
wr~ low pulse width
TBD
24*Tosc/TBD
TBD
twdsu
write data setup time to wr~ rise
TBD
24*Tosc/TBD
TBD
twdh
write data hold time after wr~ rise
TBD
8*Tosc/TBD
TBD
Tosc is one-half oscillator period
(Bus cycle = 4x oscillator period)
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