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參數(shù)資料
| 型號： | MC68HC05C0P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 53/96頁 |
| 文件大?。?/td> | 357K |
| 代理商： | MC68HC05C0P |
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MOTOROLA
Section 10: Multi-Function Timer
Page 48
MC68HC05C0 Specification Rev. 1.2
As seen in Figure 10-1 : Multi-Function Timer Block Diagram, the Timer begins with a
fixed divide-by-four prescaler. This signal drives an 8-bit ripple counter. The value of this
8-bit ripple counter can be read by the CPU at any time by accessing the Timer Counter
Register (TCR).
A timer overflow function is implemented on the last stage of this counter, giving a possible
periodic interrupt at the rate of fop/1024.
Two additional stages produce the Timer Counter Bypass circuitry, at fop/4064, (available
only in Test Mode) in the timer chain.
This circuit is followed by two more stages, with the resulting clock (fop/16384) driving the
Real Time Interrupt circuit. The RTI circuit consists of three divider stages with a 1 of 4
selector.
The output of the RTI circuit is further divided by eight to drive the COP Watchdog Timer
circuit.
The RTI rate selector bits, the RTI and TOF enable bits, the RTI and TOF flags and clearing
mechanisms are located in the Timer Control and Status Register.
The STOP mode recovery timing is selected from the fop/4064 and fop/1024 signals. The
POR function uses the fop/4064.
10.2
TIMER CONTROL AND STATUS REGISTER (TCSR)
The TCSR contains the timer interrupt flag, the timer interrupt enable bits, the timer
interrupt clearing mechanisms and the real time interrupt rate select bits. Figure 10-2 :
Timer Control and Status Register (TCSR) shows the value of each bit in the TCSR when
coming out of reset.
Figure 10-2: Timer Control and Status Register (TCSR)
10.2.1
TOF - Timer Over Flow
TOF is a read-only status bit and is set when the 8-bit ripple counter rolls over from $FF to
$00. A CPU interrupt request will be generated if TOFE is set. Clearing the TOF is done by
writing a logic 1 to TOFC. Writing to TOF has no effect. A reset clears TOF.
10.2.2
RTIF - Real Time Interrupt Flag
The Real Time Interrupt circuit consists of a three stage divider and a 1 of 4 selector. The
clock frequency that drives the RTI circuit is E/2**14 (or E/16384) with three additional
divider stages giving a maximum interrupt period of 65.5 milliseconds at a bus rate of 2
MHz. RTIF is a read-only status bit and is set when the output of the chosen (1 of 4
RD
WR
RST
76543210
TCSR
$08
0
RT0
RT1
RTIFC
TOFE
RTIE
TOFC
0
000
0
1
RTIF
TOF
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