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參數(shù)資料
| 型號： | MC68HC05C0P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 24/96頁 |
| 文件大小： | 357K |
| 代理商： | MC68HC05C0P |
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Section 4: Interrupts
MOTOROLA
Page 21
MC68HC05C0 Specification Rev. 1.2
4.4
16-BIT TIMER INTERRUPT
There are three16-Bit Timer interrupt flags that cause a timer interrupt whenever they are
set and enabled. The interrupt flags and enable bits are located in the Timer Status
Register (TSR) and the Timer Control Register (TCR) respectively. Any of these interrupts
will vector to the same interrupt service routine, located at the address specified by the
contents of memory location $FFF8 and $FFF9. See Section 11 16-BIT TIMER for more
information on the 16-Bit Timer interrupts.
4.5
SERIAL COMMUNICATIONS INTERFACE INTERRUPT
There are four Serial Communications Interface (SCI) interrupt flags that will cause an
interrupt whenever they are set and enabled. The interrupt flags and enable bits are located
in the SCI Status Register (SCSR) and the SCI Control Register2 (SCCR2) respectively.
Any of these interrupts will vector to the interrupt service routine located at the address
specified by the contents of memory locations $FFF6 and $FFF7. See Section 12 SERIAL
COMMUNICATIONS INTERFACE for more information on the SCI interrupts.
4.6
MULTI-FUNCTION TIMER INTERRUPTS
There are two Multi-Function Timer (MFT) interrupt flags that will cause an interrupt
whenever they are set and enabled. The interrupt flags and enable bits are located in the
MFT Control and Status Register (TCSR). Either of these interrupts will vector to the same
interrupt service routine, located at the address specified by the contents of memory
locations $FFF4 and $FFF5. See Section 10 MULTI-FUNCTION TIMER for more
information on MFT interrupts.
4.7
KEYBOARD SCAN INTERRUPT
Port D can be configured to enable internal pullups and generate an interrupt when any of
the 8 I/0 Lines are pulled low.
Either a level and edge-sensitive trigger option, or an edge-sensitive-only trigger option is
one-time writable (at reset) in the External Interrupt Control/Status Register. In addition,
this register also provides enable, request and acknowledge bits for the Keyboard Scan
Interrupt (KEY). A KEY interrupt will vector to the interrupt service routine, located at the
address specified by the contents of memory locations $FFF2 and $FFF3. See Section 8.3
CONFIGURATION REGISTER (CNFGR) for more details.
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