參數(shù)資料
型號： MC68HC05C0P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40
封裝： DIP-40
文件頁數(shù)： 74/96頁
文件大?。?/td> 357K
代理商： MC68HC05C0P
Section 12: Serial Communications Interface
MOTOROLA
Page 67
MC68HC05C0 Specification Rev. 1.2
12.4.3
START BIT DETECTION FOLLOWING A FRAMING ERROR
A framing error occurs if the bit stream word boundaries are not synchronized with the
receiver bit counter. If there has been a framing error without detection of a break (10 zeros
for 8-bit format or 11 zeros for 9-bit format), the circuit continues to operate as if there
actually was a stop bit. In this case the start edge may be placed artificially. See Figure
The last bit received in the data shift register (which is to be interpreted as a stop bit) will
be inverted to a logic one, and the three logic one start qualifiers (shown in Figure 12-3)
are forced into the sample shift register during the interval when detection of a start bit is
anticipated. This creates a falling edge at the appropriate time for a start bit, which will re-
synchronize the data and receiver. Example (b) does not require an artificial start because
the line returns high, therefore the start bit is created without intervention.
If the receiver detects that a break produced the framing error (RDRF=1, FE=1, receiver
data register = $00), the start bit will not be artificially induced and the receiver must actually
detect a logic one before the start bit can be recognized (See Figure 12-6 : SCI Start Bit
Figure 12-5: SCI Artificial Start Following a Framing Error
DATA
EXPECTED STOP
START BIT
RECEIVE
DATA IN
DATA SAMPLES
ARTIFICIAL EDGE
RECEIVE
DATA IN
DATA
EXPECTED STOP
DATA SAMPLES
START BIT
DATA
START EDGE
(a) LINE IS LOW AT END OF STOP BIT - SO START EDGE IS ARTIFICIALLY PLACED
IDLE
(b) LINE IS HIGH AT END OF STOP BIT - WAIT FOR REAL START EDGE
相關(guān)PDF資料
PDF描述
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