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參數(shù)資料
| 型號： | MC68HC05C0P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 73/96頁 |
| 文件大小： | 357K |
| 代理商： | MC68HC05C0P |
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MOTOROLA
Section 12: Serial Communications Interface
Page 66
MC68HC05C0 Specification Rev. 1.2
The receive clock generator is controlled by the baud rate register (See Section 12.6.5
BAUD RATE REGISTER); however, the SCI is synchronized by the start bit independent
of the transmitter.
Once a valid start bit is detected, the start bit, each data bit, and the stop bit are each
sampled three more times at intervals of 8RT, 9RT and 10RT (1RT is the position where
the bit is expected to start). See Figure 12-4 : SCI Sampling Technique used on all Bits.
The value of the bit is determined by voting logic which takes the value of a majority of
samples. A noise flag is set if all three samples on a valid start bit, data bit, or stop bit do
not agree. A noise flag is also set if the start verification samples do not agree.
Figure 12-3: SCI Examples of Start Bit Recognition Technique
Figure 12-4: SCI Sampling Technique used on all Bits
IDLE
START
0
1
2
3
4
5
6
7
IDLE
START
0
1
2
3
4
5
6
7
1
0
V
START EDGE
VERIFICATION SAMPLES
NOISE
V
START
QUALIFIERS
V
1
0
1
0
IDLE
START
0
1
2
3
4
5
6
7
1
0
1
0
NOISE
SAMPLES
PREVIOUS BIT
PRESENT BIT
NEXT BIT
V
1
RT
1
RT
16
RT
16
RT
RDI
8
RT
9
RT
10
RT
VV
SAMPLES
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