- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45218 > MC68HC05C0P (MOTOROLA INC) 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40 PDF資料下載
參數(shù)資料
| 型號： | MC68HC05C0P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 50/96頁 |
| 文件大?。?/td> | 357K |
| 代理商： | MC68HC05C0P |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
Section 9: Address/Data Bus Interface
MOTOROLA
Page 45
MC68HC05C0 Specification Rev. 1.2
9.5
BUS CYCLE CHARACTERISTICS
There are a few points to be made regarding bus activity which are independent of mode
or cycle stretching. First, as in all 68HC05 microcontrollers, any write cycle is preceded by
a “dummy” read cycle. Although this is transparent to the user with other 68HC05 parts, the
68HC05C0 expanded bus reveals this phenomena. Another note of interest is that if IRV is
not enabled, internal bus activity does not cause changes on the external address or data
pins, or the RD, WR or chip select outputs. See Section 8.3.4 IRV - Internal Read Visibility
for more information on IRV. The reason for this behavior is to reduce unnecessary external
switching which contributes to power consumption and noise. For the same reasons,
effective address calculation bus cycles which force the internal address bus to $XXFE are
not reflected externally, unless IRV is enabled.
9.6
ADDRESS/DATA BUS DURING WAIT AND STOP MODE
The CPU halts during WAIT or STOP mode, which suspends bus activity. The address bus
will hold the state of the address following the WAIT or STOP instruction. If the part is
operating in Muxed Mode, the muxed address/data bus is driven with the lower order
address following the WAIT or STOP instruction. If the part is operating in Non-Muxed
Mode, the data bus will be driven to the opcode of the instruction following the WAIT or
STOP instruction. When the processor exits WAIT or STOP mode, the bus activity will
resume.
NOTE:
When executing a program out of external memory, RD will remain low
during STOP mode and will become high again at the beginning of the
STOP recovery. This implies that the external memory will be driving data
for the duration of STOP. If it is not desired that the external memory be
active for the entire STOP duration, the STOP instruction should be
executed out of internal RAM with internal read visibility disabled.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05C0FN | 8-BIT, 4 MHz, MICROCONTROLLER, PQCC44 |
| MC68HC05C12AFN | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| MC68HSC05C12AB | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP42 |
| MC68HSC05C12ACP | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP40 |
| MC68HC05C12ACFN | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05C12 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
| MC68HC05C12B | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
| MC68HC05C12CP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
| MC68HC05C12P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
| MC68HC05C4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcomputers |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。