參數(shù)資料
型號(hào)： MC68HC05C0P
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40
封裝： DIP-40
文件頁(yè)數(shù)： 70/96頁(yè)
文件大?。?/td> 357K
代理商： MC68HC05C0P
Section 12: Serial Communications Interface
MOTOROLA
Page 63
MC68HC05C0 Specification Rev. 1.2
Data transmission is initiated by a write to the serial communications data register
(SCDAT). Provided the transmitter is enabled, data stored in the SCDAT is transferred to
the transmit data shift register. This transfer of data sets the transmit data register empty
flag (TDRE) in the SCI status register (SCSR) and may generate an interrupt if the transmit
interrupt is enabled. The transfer of data to the transmit data shift register is synchronized
with the bit rate clock. All data is transmitted least significant bit first. Upon completion of
data transmission, the transmission complete flag (TC) in the SCSR is set (provided no
pending data, preamble or break is to be sent), and an interrupt may be generated if the
transmit complete interrupt is enabled. The TC bit will also be set if the transmitter is
disabled, and the data, preamble or break (in the transmit data shift register) has been sent.
This will also generate an interrupt if the transmission complete interrupt enable bit (TCIE)
is set. If the transmitter is disabled in the middle of a transmission, that character will be
completed before the transmitter gives up control of the TDO pin.
The data transfer from the input serial shift register to the SCDAT is synchronized by the
receiver bit rate clock. The receive data register full flag bit (RDRF) in the SCSR is set to
indicate that a data byte has been transferred from the input serial shift register to the
SCDAT, which can cause an interrupt if the receiver interrupt is enabled.
The OR
(overrun), NF (noise), or FE (framing) error flags in the SCSR may be set if data reception
errors occurred. When SCDAT is read, it contains the last data byte received, provided that
the receiver is enabled.
An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which
detects idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-
up mode to detect the end of a message or the preamble of a new message, or to
resynchronize with the transmitter. A valid character must be received before the idle line
condition or the IDLE bit will not be set and idle line interrupt will not be generated.
相關(guān)PDF資料
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