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參數(shù)資料
| 型號(hào)： | MC68HC05G3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 102/128頁 |
| 文件大小： | 290K |
| 代理商： | MC68HC05G3 |
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Page 65
Section 7: SERIAL PERIPHERAL INTERFACE (SPI)
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
SECTION 7
SERIAL PERIPHERAL INTERFACE (SPI)
Two serial peripheral interfaces (SPI) are built into the MC68HC05G3 (705G4).
In the SPI format, three separate wires are required for data input, output, and clock. In this
format, the clock is not being included in the data stream and must be provided as a
separate signal. The three pins are occupied for serial clock, input data, and output data.
When one of the SPIs is enabled (SPE = 1), bit 0 through bit 2 of port C/port G become
SDI, SDO, and SCK pins, and the corresponding DDRC/DDRG bit has no affect on the
direction of the pin.
The MSTR bit decides the SPI operation mode; SCK pin is configured as output in the
master mode and configured as input in the slave mode.
The DORD bit in the serial peripheral control register (SPCR) selects the data transmission
order. When DORD bit is set, the LSB of serial data is shifted out/in first. When the DORD
bit is clear, serial data is shifted from MSB.
Serial clock speed is selectable by the SPR bit in the SPCR. Interrupt may be generated
by the completion of transfer.
7.1
FEATURES
Full Duplex, Three-Wire Synchronous Transfers
Master and Slave Operation
Programmable Data Transmission Order
E/2 (Maximum) Master Bit Frequency
E (Maximum) Slave Bit Frequency
Two Programmable Master Bit Rates
End of Transmission Interrupt Flag
Wakeup from Stop Mode (Slave Mode Only)
7.2
FUNCTIONAL DESCRIPTIONS
A block diagram of the serial peripheral is shown in Figure 7-2.
The clock start logic is triggered by CPU (detection of CPU write to the 8-bit shift register
(SPDR)) and originates the system clock (SCK) based on the internal processor clock. This
clock also is used in the 3-bit counter and 8-bit shift register.
After data is written to the 8-bit shift register of the master device, it is then shifted out to
the SDO pin for application to the slave device. At the same time, data applied from a slave
device via the SDI pin is shifted into the 8-bit shift register.
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