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參數(shù)資料
| 型號： | MC68HC05G3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 98/128頁 |
| 文件大?。?/td> | 290K |
| 代理商： | MC68HC05G3 |
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Page 61
Section 6: INPUT/OUTPUT PORTS
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
6.7
PORT G
Port G pins share the functions with several on-chip peripherals. A pin function is controlled
by the enable bit of each associated peripheral.
PG7 through PG4 are general-purpose I/O pins and PWM output pins. When the PWM is
enabled, one or more of the channels, PG7 through PG4, will be configured as a PWM
output pin regardless of the state of DDRG7 through DDRG4. The DDRG7 through DDRG4
bits determine the CPU read of the PORTG register (pin states for the input configuration
or data latch for the output configuration).
The PG3 pin shares function with the timer output pin (TCMP). When PG3 is configured as
an output, it will be tied to the TCMP and cannot be used to provide output from the data
register. The PG3 pin state always will be read by the CPU, regardless of the state of
DDRG3.
The PG2 through PG0 pins are shared with the serial peripheral interface (SPI2). When the
SPI2 is not used (SPE2 = 0), DDRG2 through DDRG0 bits control the directions of the pins,
and when the SPI2 is enabled, the pins are configured as serial clock output or input
(SCK2), serial data output (SDO2), and serial data input (SDI2). The direction of the SCK2
depends on the MSTR2 bit in the SPCR2. The DDRG2 through DDRG0 bits always affect
the CPU read of PORTG register (pin states for the input configuration or data latch for the
output configuration.)
Open drain or CMOS outputs are selected by GWOMH and GWOML bits in the WOM1
register. If the GWOMH bit is set, the P-channel drivers of output buffers of bit 7 through bit
4 are disabled (open drain). If the GWOML bit is set, the P-channel drivers of output buffers
of bit 3 through bit 0 are disabled (open drain). These open drain or CMOS output options
are effective to either the general-purpose outputs or the peripheral outputs (PWM, TCMP,
SCK2, and SDO2).
Port G has pullup resistors as an option. When the RGH or RGL bit in the RCR1 is set, the
pullup resistors are attached to the upper four bits or lower four bits of port G pins. (The
typical resistor values are to be 10 K
@ 3 V.) When a pin outputs a low level, the pullup
resistor is disconnected regardless of the states of the RGH or RGL bits.
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