參數(shù)資料
型號: MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 104/128頁
文件大?。?/td> 290K
代理商: MC68HC05G3
Page 67
Section 7: SERIAL PERIPHERAL INTERFACE (SPI)
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
CONTROL
This block is an interface to the HC05 internal bus and generates a START
signal when writing to SPDR is detected in the master mode. It also
generates an interrupt request to the CPU.
SPDR
This register is an 8-bit shift register called serial peripheral data register
(SPDR). The DORD bit in the SPCR determines the bus connection between
internal data bus and SPDR. This register can be read and written by the
CPU.
SPCR
Serial peripheral control register (SPCR). The bits in this register control SPI
functions.
SPSR
Serial peripheral status register (SPSR). This register mainly sets flags such
as SPIF and DCOL.
CLKGEN
In the master mode, this block generates serial clock (SCK) when CPU writes
to data register (SPDR) and the clock rate is selected by SPR bit in the control
register.
In slave mode, external clock from SCK pin is used instead of master mode
clock and SPR has no affect on SCK.
This clock generator includes a 3-bit clock counter. Overflow of this counter
sets SPIF.
相關PDF資料
PDF描述
MC68HC705J5ACJP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP16
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