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參數(shù)資料
| 型號： | MC68HC05G3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 77/128頁 |
| 文件大?。?/td> | 290K |
| 代理商： | MC68HC05G3 |
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Page 42
MOTOROLA
Section 4: CPU CORE
MC68HC05G3 (705G4) Specification Rev. 1.1
4.4
LOW-POWER MODES
The MC68HC05G3 (705G4) has two power-saving modes, stop and wait. Flowcharts of
these modes are shown in Figure 4-3: STOP/WAIT Flowcharts.
4.4.1
STOP MODE
The STOP instruction places the MCU in its lowest power consumption mode. During stop
mode, the internal main oscillator (OSC) is turned off and the clock pass from the second
oscillator (XOSC) is disconnected, so that all modules except time base are halted. The
sub-oscillator (XOSC) does not stop oscillating. Therefore, if XOSC is used as the clock
source for COP, COP still is functional in stop mode.
During stop mode, the I bit in the CCR is cleared to enable external interrupts. All other
registers and memory remain unaltered. All input/output lines remain unchanged. The stop
mode is exited by RESET or by receipt of an interrupt from IRQ1/2, KWI, SPI1/2 (slave
mode only), or TBI (when XOSC is selected as time base clock). Refer to 1.4.1
OSCILLATORS AND CLOCK DISTRIBUTIONS for more information during stop mode.
4.4.2
WAIT MODE
The WAIT instruction places the MCU in a low-power consumption mode, but the wait
mode consumes more power than the stop mode. In the wait mode, only the CPU clocks
are halted and it never affects the peripheral modules. During the wait mode, the I bit in the
CCR is cleared to enable interrupts. All other registers, memory, and input/output lines
remain in their previous state. The wait mode is exited by RESET and any interrupts. The
on-chip oscillator (OSC and XOSC) circuit remains active throughout the wait standby
period.
The reduction of power in the wait mode depends on how many of the on-chip peripheral
functions can be shut down (clocks). The CPU always shuts down in the wait mode. The
peripherals are enabled or disabled based upon their control bits. (The time base clock
dividers are always enabled.)
It should be obvious that the amount of power that will be consumed is dependant on the
particular application and that it would be prohibitive to test all parts for all variations. For
these reasons, the data sheet will include values for a limited number of variations. These
variations and the corresponding MAX power consumptions will be decided after the initial
characterization of the silicon.
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