參數(shù)資料
型號： MC68HC05G3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 15/128頁
文件大?。?/td> 290K
代理商： MC68HC05G3
Page 101
Section 9: PULSE WIDTH MODULATOR
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
A brief operational description of a PWM channel: An 8-bit counter runs at the rate of the
selected clock source, as described earlier. When all channels are disabled, the counter is
preset to $FF. Once the channel(s) is enabled, the counter begins incrementing. When this
counter overflows, three things happen: the counter presets to $01, a flip-flop is set causing
the PWM output to go high, and the latched value in the duty register is transferred to the
buffer. A match (MTH) between the counter and the duty register buffer resets the flip-flop,
thus giving a low output. A value $00 written into the duty register buffer triggers the zero
detector to hold the reset on the flip-flop.
9.2
PWM CONTROL REGISTER (PWMCR)
Each channel of the PWM is enabled by a bit in the PWMCR register.
Each PWM output pin is shared with a general programmable port I/O bit. When the PWM
output control bit (CH
x) is set to one, the associated port G line will function as a PWM
output regardless of the state of the associated DDRG bit. This does not change the state
of the DDR bit, and when CH
x is disabled the DDRGx bit again controls the I/O state. CHx
is cleared on reset to prevent erroneous output.
9.3
PWM DUTY REGISTER (PWMDR
x)
The PWM has four duty registers associated with it: $36 - $39, PWMDR0 - PWMDR3.
Reads of this register return the most recent written value.
Each output is a pulse width modulated signal whose duty cycle varies according to the
value set into its duty register. The duty cycle is expressed with eight bits of resolution. The
signal can be used directly as a PWM signal, or it may be filtered to obtain an average value
for a general-purpose analog output.
The repetition rate is 255 times the programmable timer clock overflow rate. (For example,
the repetition rate for a 4.00 MHz crystal (2 MHz internal clock) is 7843 Hz.) A value of $00
loaded into the duty register results in a continuous low output on the corresponding PWM
output pin. A value of $7F or $80 results in approximately 50% duty cycle output, and so
on, to the maximum value, $FF, which corresponds to an output which is at 1 for 255/255
of the cycle. If the register PWMDR
x is written while the channel is enabled, the new value
will be picked up by the PWM converters only at the end of a complete conversion cycle.
Figure 9-2: PWM Control Registers
0
$0034
0
CH3
CH2
CH1
CH0
PWMCR
B7
B6
B5
B4
B3
B2
B1
B0
00000000
RESET:
Figure 9-3: PWM Duty Registers
$36-39
PWMDR
x
B7
B6
B5
B4
B3
B2
B1
B0
00000000
RESET:
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