參數(shù)資料
型號: MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 121/128頁
文件大?。?/td> 290K
代理商: MC68HC05G3
Page 82
MOTOROLA
Section 8: TIMER SYSTEM
MC68HC05G3 (705G4) Specification Rev. 1.1
8.1.5
TIMER STATUS REGISTER (TSR) $13
The TSR is a read-only register containing three status flag bits.
READ:
anytime
WRITE:
no effect
ICF
Input Capture Flag
1 - Flag set when selected polarity edge is sensed by input capture edge
detector
0 - Flag cleared when TSR and input capture low register ($15) are
accessed
OC1F
Output Compare 1 Flag
1 - Flag set when output compare register contents match the free-running
counter contents
0 - Flag cleared when TSR and output compare low register ($17) are
accessed
TOF
Timer Overflow Flag
1 - Flag set when free-running counter transition from $FFFF to $0000
occurs
0 - Flag cleared when TSR and counter low register ($19) are accessed
BITS 0-4
Not used
Always read zero
Accessing the timer status register satisfies the first condition required to clear status bits.
The remaining step is to access the register corresponding to the status bit.
A problem can occur when using the timer overflow function and reading the free-running
counter at random times to measure an elapsed time. Without incorporating the proper
precautions into software, the timer overflow flag could be cleared unintentionally if:
1) The timer status register is read or written when TOF is set, and
2) The LSB of the free-running counter is read but not for the purpose of servicing the
flag.
The counter alternate register at address $1A and $1B contains the same value as the free-
running counter (at address $18 and $19); therefore, this alternate register can be read at
any time without affecting the timer overflow flag in the timer status register.
ICF
$0013
OC1F
TOF
0
TSR
B7
B6
B5
B4
B3
B2
B1
B0
U
00000
RESET:
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